diff --git a/build.sbt b/build.sbt index 52738370..3a48cd3a 100644 --- a/build.sbt +++ b/build.sbt @@ -8,7 +8,7 @@ ThisBuild / publishTo := Some(Opts.resolver.sonatypeStaging) ThisBuild / resolvers += "jitpack" at "https://jitpack.io" -lazy val forsydeIoVersion = "develop-SNAPSHOT" +lazy val forsydeIoVersion = "0.7.14" lazy val jgraphtVersion = "1.5.1" lazy val scribeVersion = "3.10.2" lazy val scalaGraphVersion = "1.13.5" diff --git a/java-blueprints/src/main/java/idesyde/blueprints/StandaloneIdentificationModule.java b/java-blueprints/src/main/java/idesyde/blueprints/StandaloneIdentificationModule.java index d0a4b28a..48632028 100644 --- a/java-blueprints/src/main/java/idesyde/blueprints/StandaloneIdentificationModule.java +++ b/java-blueprints/src/main/java/idesyde/blueprints/StandaloneIdentificationModule.java @@ -145,16 +145,43 @@ default Optional standaloneIdentificationModule( ctx.status(500); } }) - .get( - "/integrate", + .post( + "/reverse", ctx -> { - var integrated = reverseIdentification( - globalSolvedDecisionModels, - globalDesignModels); - ctx.result(objectMapper.writeValueAsString(integrated - .stream() - .map(x -> DesignModelMessage.from(x)) - .collect(Collectors.toList()))); + if (ctx.isMultipartFormData()) { + var decisionModels = new HashSet(); + var designModels = new HashSet(); + ctx.formParamMap().forEach((name, entries) -> { + if (name.startsWith("decisionModel")) { + for (var msg : entries) { + DecisionModelMessage + .fromJsonString(msg) + .flatMap(this::decisionMessageToModel) + .ifPresent(decisionModels::add); + } + } else if (name.startsWith( + "designModel")) { + for (var msg : entries) { + DesignModelMessage + .fromJsonString(msg) + .flatMap(this::designMessageToModel) + .ifPresent(designModels::add); + + } + } + }); + var integrated = reverseIdentification( + decisionModels, designModels); + ctx.result(objectMapper + .writeValueAsString(integrated + .stream() + .map(x -> DesignModelMessage + .from(x)) + .collect(Collectors + .toList()))); + } else { + ctx.status(500); + } }) .exception( Exception.class, diff --git a/java-bridge-forsyde-io/build.gradle b/java-bridge-forsyde-io/build.gradle index 2ef54d6c..5beedbe2 100644 --- a/java-bridge-forsyde-io/build.gradle +++ b/java-bridge-forsyde-io/build.gradle @@ -2,7 +2,7 @@ plugins { id 'idesyde.java-standalone-imodule' } -def forsydeioVersion = "develop-SNAPSHOT" +def forsydeioVersion = "0.7.14" dependencies { testImplementation 'org.junit.jupiter:junit-jupiter-api:5.8.1' diff --git a/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticoreReverseIdentification.java b/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticoreReverseIdentification.java index 552a193c..f16855e3 100644 --- a/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticoreReverseIdentification.java +++ b/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticoreReverseIdentification.java @@ -12,95 +12,98 @@ import forsyde.io.lib.hierarchy.ForSyDeHierarchy; public class AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticoreReverseIdentification - implements ReverseIdentificationRule { + implements ReverseIdentificationRule { - private Set innerReverseIdentifyAperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore( - Set solvedModels, - Set designModels) { - return solvedModels.stream().map(model -> { - var reversedSystemGraph = new SystemGraph(); - model.processesToMemoryMapping().forEach((process, mem) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(process).stream()).findAny() - .ifPresent(procVertex -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(mem).stream()).findAny() - .ifPresent(memVertex -> { - reversedSystemGraph.addVertex(procVertex); - reversedSystemGraph.addVertex(memVertex); - var memMapped = ForSyDeHierarchy.MemoryMapped.enforce(reversedSystemGraph, - procVertex); - memMapped.mappingHost(ForSyDeHierarchy.GenericMemoryModule - .enforce(reversedSystemGraph, memVertex)); - ForSyDeHierarchy.GreyBox.enforce(reversedSystemGraph, memVertex) - .addContained(ForSyDeHierarchy.Visualizable.enforce(memMapped)); - }); + private Set innerReverseIdentifyAperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore( + Set solvedModels, + Set designModels) { + return solvedModels.stream().map(model -> { + var reversedSystemGraph = new SystemGraph(); + model.processesToMemoryMapping().forEach((process, mem) -> { + var procVertex = reversedSystemGraph.newVertex(process); + var memVertex = reversedSystemGraph.newVertex(mem); + var memMapped = ForSyDeHierarchy.MemoryMapped + .enforce(reversedSystemGraph, + procVertex); + memMapped.mappingHost( + ForSyDeHierarchy.GenericMemoryModule + .enforce(reversedSystemGraph, + memVertex)); + ForSyDeHierarchy.GreyBox.enforce( + reversedSystemGraph, + memVertex) + .addContained(ForSyDeHierarchy.Visualizable + .enforce(memMapped)); }); - }); - model.bufferToMemoryMappings().forEach((buf, mem) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(buf).stream()).findAny() - .ifPresent(procVertex -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(mem).stream()).findAny() - .ifPresent(memVertex -> { - reversedSystemGraph.addVertex(procVertex); - reversedSystemGraph.addVertex(memVertex); - var memMapped = ForSyDeHierarchy.MemoryMapped.enforce(reversedSystemGraph, - procVertex); - memMapped.mappingHost(ForSyDeHierarchy.GenericMemoryModule - .enforce(reversedSystemGraph, memVertex)); - ForSyDeHierarchy.GreyBox.enforce(reversedSystemGraph, memVertex) - .addContained(ForSyDeHierarchy.Visualizable.enforce(memMapped)); - }); + model.bufferToMemoryMappings().forEach((buf, mem) -> { + var bufVertex = reversedSystemGraph.newVertex(buf); + var memVertex = reversedSystemGraph.newVertex(mem); + var memMapped = ForSyDeHierarchy.MemoryMapped + .enforce(reversedSystemGraph, + bufVertex); + memMapped.mappingHost( + ForSyDeHierarchy.GenericMemoryModule + .enforce(reversedSystemGraph, + memVertex)); + ForSyDeHierarchy.GreyBox.enforce( + reversedSystemGraph, + memVertex) + .addContained(ForSyDeHierarchy.Visualizable + .enforce(memMapped)); }); - }); - model.processesToRuntimeScheduling().forEach((process, sched) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(process).stream()).findAny() - .ifPresent(procVertex -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(sched).stream()).findAny() - .ifPresent(schedVertex -> { - reversedSystemGraph.addVertex(procVertex); - reversedSystemGraph.addVertex(schedVertex); - var scheduled = ForSyDeHierarchy.Scheduled.enforce(reversedSystemGraph, - procVertex); - scheduled.runtimeHost(ForSyDeHierarchy.AbstractRuntime - .enforce(reversedSystemGraph, schedVertex)); - ForSyDeHierarchy.GreyBox.enforce(reversedSystemGraph, schedVertex) - .addContained(ForSyDeHierarchy.Visualizable.enforce(scheduled)); - }); + model.processesToRuntimeScheduling().forEach((process, sched) -> { + var procVertex = reversedSystemGraph.newVertex(process); + var schedVertex = reversedSystemGraph.newVertex(sched); + var scheduled = ForSyDeHierarchy.Scheduled + .enforce(reversedSystemGraph, + procVertex); + scheduled.runtimeHost( + ForSyDeHierarchy.AbstractRuntime + .enforce(reversedSystemGraph, + schedVertex)); + ForSyDeHierarchy.GreyBox.enforce( + reversedSystemGraph, + schedVertex) + .addContained(ForSyDeHierarchy.Visualizable + .enforce(scheduled)); }); - }); - model.superLoopSchedules().forEach((sched, looplist) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(sched).stream()).findAny() - .ifPresent(schedVertex -> { - var scheduler = ForSyDeHierarchy.SuperLoopRuntime.enforce(reversedSystemGraph, schedVertex); - scheduler.superLoopEntries(looplist); + model.superLoopSchedules().forEach((sched, looplist) -> { + var schedVertex = reversedSystemGraph.newVertex(sched); + var scheduler = ForSyDeHierarchy.SuperLoopRuntime + .enforce(reversedSystemGraph, schedVertex); + scheduler.superLoopEntries(looplist); }); - }); - model.aperiodicAsynchronousDataflows() - .forEach(app -> app.processMinimumThroughput().entrySet().forEach(e -> { - var process = reversedSystemGraph.queryVertex(e.getKey()) - .orElse(reversedSystemGraph.newVertex(e.getKey())); - var behaviour = ForSyDeHierarchy.AnalyzedBehavior - .enforce(reversedSystemGraph, process); - var scale = 1.0; - while (Math.ceil(e.getValue() * scale) - - (e.getValue() * scale) > 0.0001) { - scale *= 10.0; + model.aperiodicAsynchronousDataflows() + .forEach(app -> app.processMinimumThroughput().entrySet().forEach(e -> { + var process = reversedSystemGraph.queryVertex(e.getKey()) + .orElse(reversedSystemGraph.newVertex(e.getKey())); + var behaviour = ForSyDeHierarchy.AnalyzedBehavior + .enforce(reversedSystemGraph, process); + var scale = 1.0; + while (Math.ceil(e.getValue() * scale) + - (e.getValue() * scale) > 0.0001) { + scale *= 10.0; + } + behaviour.setThroughputInSecsDenominator((long) (e.getValue() * scale)); + behaviour.setThroughputInSecsNumerator((long) scale); + })); + for (var x : designModels) { + reversedSystemGraph.mergeInPlace(x.systemGraph()); } - behaviour.setThroughputInSecsDenominator((long) (e.getValue() * scale)); - behaviour.setThroughputInSecsNumerator((long) scale); - })); - return new ForSyDeIODesignModel(reversedSystemGraph); - }).collect(Collectors.toSet()); - } + return new ForSyDeIODesignModel(reversedSystemGraph); + }).collect(Collectors.toSet()); + } - @Override - public Set apply(Set t, Set u) { - var filteredSolved = t.stream() - .filter(x -> x instanceof AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore) - .map(x -> (AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore) x) - .collect(Collectors.toSet()); - var filteredDesign = u.stream().filter(x -> x instanceof ForSyDeIODesignModel) - .map(x -> (ForSyDeIODesignModel) x).collect(Collectors.toSet()); - return innerReverseIdentifyAperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore(filteredSolved, - filteredDesign); - } + @Override + public Set apply(Set t, Set u) { + var filteredSolved = t.stream() + .filter(x -> x instanceof AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore) + .map(x -> (AperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore) x) + .collect(Collectors.toSet()); + var filteredDesign = u.stream().filter(x -> x instanceof ForSyDeIODesignModel) + .map(x -> (ForSyDeIODesignModel) x).collect(Collectors.toSet()); + return innerReverseIdentifyAperiodicAsynchronousDataflowToPartitionedMemoryMappableMulticore( + filteredSolved, + filteredDesign); + } } diff --git a/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedTiledMulticoreReverseIdentification.java b/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedTiledMulticoreReverseIdentification.java index 85fa2b93..bef27d6c 100644 --- a/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedTiledMulticoreReverseIdentification.java +++ b/java-bridge-forsyde-io/src/main/java/idesyde/forsydeio/AperiodicAsynchronousDataflowToPartitionedTiledMulticoreReverseIdentification.java @@ -18,104 +18,65 @@ private Set innerReverseIdentifyAperiodicAsynchronousDataflowToPart Set solvedModels, Set designModels) { return solvedModels.stream().map(model -> { - var reversedSystemGraph = new SystemGraph(); + SystemGraph reversedSystemGraph = new SystemGraph(); model.processesToMemoryMapping().forEach((process, mem) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(process).stream()) - .findAny() - .ifPresent(procVertex -> { - designModels.stream() - .flatMap(m -> m.systemGraph().queryVertex(mem) - .stream()) - .findAny() - .ifPresent(memVertex -> { - reversedSystemGraph - .addVertex(procVertex); - reversedSystemGraph - .addVertex(memVertex); - var memMapped = ForSyDeHierarchy.MemoryMapped - .enforce(reversedSystemGraph, - procVertex); - memMapped.mappingHost( - ForSyDeHierarchy.GenericMemoryModule - .enforce(reversedSystemGraph, - memVertex)); - ForSyDeHierarchy.GreyBox.enforce( - reversedSystemGraph, - memVertex) - .addContained(ForSyDeHierarchy.Visualizable - .enforce(memMapped)); - }); - }); + var procVertex = reversedSystemGraph.newVertex(process); + var memVertex = reversedSystemGraph.newVertex(mem); + var memMapped = ForSyDeHierarchy.MemoryMapped + .enforce(reversedSystemGraph, + procVertex); + memMapped.mappingHost( + ForSyDeHierarchy.GenericMemoryModule + .enforce(reversedSystemGraph, + memVertex)); + ForSyDeHierarchy.GreyBox.enforce( + reversedSystemGraph, + memVertex) + .addContained(ForSyDeHierarchy.Visualizable + .enforce(memMapped)); }); model.bufferToMemoryMappings().forEach((buf, mem) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(buf).stream()).findAny() - .ifPresent(procVertex -> { - designModels.stream() - .flatMap(m -> m.systemGraph().queryVertex(mem) - .stream()) - .findAny() - .ifPresent(memVertex -> { - reversedSystemGraph - .addVertex(procVertex); - reversedSystemGraph - .addVertex(memVertex); - var memMapped = ForSyDeHierarchy.MemoryMapped - .enforce(reversedSystemGraph, - procVertex); - memMapped.mappingHost( - ForSyDeHierarchy.GenericMemoryModule - .enforce(reversedSystemGraph, - memVertex)); - ForSyDeHierarchy.GreyBox.enforce( - reversedSystemGraph, - memVertex) - .addContained(ForSyDeHierarchy.Visualizable - .enforce(memMapped)); - }); - }); + var bufVertex = reversedSystemGraph.newVertex(buf); + var memVertex = reversedSystemGraph.newVertex(mem); + var memMapped = ForSyDeHierarchy.MemoryMapped + .enforce(reversedSystemGraph, + bufVertex); + memMapped.mappingHost( + ForSyDeHierarchy.GenericMemoryModule + .enforce(reversedSystemGraph, + memVertex)); + ForSyDeHierarchy.GreyBox.enforce( + reversedSystemGraph, + memVertex) + .addContained(ForSyDeHierarchy.Visualizable + .enforce(memMapped)); }); model.processesToRuntimeScheduling().forEach((process, sched) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(process).stream()) - .findAny() - .ifPresent(procVertex -> { - designModels.stream() - .flatMap(m -> m.systemGraph().queryVertex(sched) - .stream()) - .findAny() - .ifPresent(schedVertex -> { - reversedSystemGraph - .addVertex(procVertex); - reversedSystemGraph - .addVertex(schedVertex); - var scheduled = ForSyDeHierarchy.Scheduled - .enforce(reversedSystemGraph, - procVertex); - scheduled.runtimeHost( - ForSyDeHierarchy.AbstractRuntime - .enforce(reversedSystemGraph, - schedVertex)); - ForSyDeHierarchy.GreyBox.enforce( - reversedSystemGraph, - schedVertex) - .addContained(ForSyDeHierarchy.Visualizable - .enforce(scheduled)); - }); - }); + var procVertex = reversedSystemGraph.newVertex(process); + var schedVertex = reversedSystemGraph.newVertex(sched); + var scheduled = ForSyDeHierarchy.Scheduled + .enforce(reversedSystemGraph, + procVertex); + scheduled.runtimeHost( + ForSyDeHierarchy.AbstractRuntime + .enforce(reversedSystemGraph, + schedVertex)); + ForSyDeHierarchy.GreyBox.enforce( + reversedSystemGraph, + schedVertex) + .addContained(ForSyDeHierarchy.Visualizable + .enforce(scheduled)); }); model.superLoopSchedules().forEach((sched, looplist) -> { - designModels.stream().flatMap(m -> m.systemGraph().queryVertex(sched).stream()) - .findAny() - .ifPresent(schedVertex -> { - var scheduler = ForSyDeHierarchy.SuperLoopRuntime - .enforce(reversedSystemGraph, schedVertex); - scheduler.superLoopEntries(looplist); - }); + var schedVertex = reversedSystemGraph.newVertex(sched); + var scheduler = ForSyDeHierarchy.SuperLoopRuntime + .enforce(reversedSystemGraph, schedVertex); + scheduler.superLoopEntries(looplist); }); model.aperiodicAsynchronousDataflows() .forEach(app -> app.processes().forEach(process -> { var th = app.processMinimumThroughput().get(process); - var processVertex = reversedSystemGraph.queryVertex(process) - .orElse(reversedSystemGraph.newVertex(process)); + var processVertex = reversedSystemGraph.newVertex(process); var behaviour = ForSyDeHierarchy.AnalyzedBehavior .enforce(reversedSystemGraph, processVertex); // var scale = 1.0; @@ -125,6 +86,11 @@ private Set innerReverseIdentifyAperiodicAsynchronousDataflowToPart behaviour.setThroughputInSecsDenominator(Math.round(th)); behaviour.setThroughputInSecsNumerator(1L); })); + // mereg HAS to come here; otherwise the vertex that java has a pointer too will + // be reused. + for (var x : designModels) { + reversedSystemGraph.mergeInPlace(x.systemGraph()); + } return new ForSyDeIODesignModel(reversedSystemGraph); }).collect(Collectors.toSet()); } diff --git a/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPMMMWithJenetics.java b/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPMMMWithJenetics.java index 38dddae0..014d4001 100644 --- a/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPMMMWithJenetics.java +++ b/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPMMMWithJenetics.java @@ -109,7 +109,7 @@ default InvertibleCodec k, - k -> IntStream.range(0, gt.get(4).length()).boxed() + k -> IntStream.range(0, jobOrderings.length()).boxed() .filter(idx -> taskScheduling .get(jobs.get(idx).process()) .equals(k)) @@ -180,6 +180,8 @@ default InvertibleCodec { var entry = looplist.get(entryI); + // this gets the first instance of a process that is still not + // scheduled and assigns it to the ordering encoding IntStream.range(0, jobs.size()) .filter(j -> model .processesToRuntimeScheduling() diff --git a/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPTMWithJenetics.java b/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPTMWithJenetics.java index 2f3e4213..7d9ee98a 100644 --- a/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPTMWithJenetics.java +++ b/java-metaheuristics/src/main/java/idesyde/metaheuristics/CanExploreAADPTMWithJenetics.java @@ -105,6 +105,10 @@ default InvertibleCodec x.allele()) + // .map(x -> x.toString()).reduce((a, b) -> a + ", " + b)); Map> superLoopSchedules = scheds.stream() .collect(Collectors.toMap( k -> k, @@ -123,6 +127,7 @@ default InvertibleCodec jobs.get(idx) .process()) .collect(Collectors.toList()))); + // System.out.println(superLoopSchedules.toString()); return new AperiodicAsynchronousDataflowToPartitionedTiledMulticore( decisionModel.aperiodicAsynchronousDataflows(), decisionModel.partitionedTiledMulticore(), @@ -139,7 +144,7 @@ default InvertibleCodec IntegerGene.of( - mems.indexOf(e.getValue()), 1, + mems.indexOf(e.getValue()), 0, mems.size())) .collect(ISeq.toISeq())); var maxReservations = decisionModel.partitionedTiledMulticore().hardware() @@ -172,12 +177,15 @@ default InvertibleCodec { var entry = looplist.get(entryI); + // this gets the first instance of a process that is still not + // scheduled and assigns it to the ordering encoding IntStream.range(0, jobs.size()) .filter(j -> model .processesToRuntimeScheduling() - .get(entry) == sched + .get(entry).equals(sched) && orderings[j] == -1 - && jobs.get(j).process() == entry) + && jobs.get(j).process() + .equals(entry)) .boxed() .min((a, b) -> (int) jobs.get(a).instance() - (int) jobs.get(b).instance()) @@ -186,7 +194,7 @@ default InvertibleCodec IntegerGene.of(orderings[j], 1, jobs.size())) + .mapToObj(j -> IntegerGene.of(orderings[j], 0, jobs.size())) .collect(ISeq.toISeq())); return Genotype.of(taskMappingChromossome, channelReservationsChromossome, jobOrderingChromossome); @@ -668,7 +676,7 @@ default double recomputeExecutionTransferTime( .processorAffinities() .get(dstPE); if (decisionModel.processesToRuntimeScheduling().get(dst.process()) - .equals(dstSched)) { // a task + .equals(dstSched) && srcPE != dstPE) { // a task double singleBottleNeckBW = decisionModel .partitionedTiledMulticore() .hardware() diff --git a/java-metaheuristics/src/main/java/idesyde/metaheuristics/constraints/AperiodicAsynchronousDataflowJobOrderingConstraint.java b/java-metaheuristics/src/main/java/idesyde/metaheuristics/constraints/AperiodicAsynchronousDataflowJobOrderingConstraint.java index 5400af35..91bd9a7e 100644 --- a/java-metaheuristics/src/main/java/idesyde/metaheuristics/constraints/AperiodicAsynchronousDataflowJobOrderingConstraint.java +++ b/java-metaheuristics/src/main/java/idesyde/metaheuristics/constraints/AperiodicAsynchronousDataflowJobOrderingConstraint.java @@ -85,19 +85,34 @@ public boolean test(Phenotype individual) { // the second checks whether they follow the parial order in the following way: // isSucessor(j, jj) -> order(j) < order(jj) // equivalently, - var isValid = mappedJobs.length == 0 || Arrays.stream(mappedJobs) - .allMatch(j -> Arrays.stream(mappedJobs) - .filter(jj -> j != jj) - .allMatch(jj -> (jobOrderings.get(j) - .allele() != jobOrderings.get(jj) - .allele()) - && - (!memoizedSucessors.get(jobs.get(j)) - .contains(jobs.get(jj)) - || jobOrderings.get(j) - .allele() < jobOrderings - .get(jj) - .allele()))); + for (var j : mappedJobs) { + for (var jj : mappedJobs) { + if (j != jj) { + if (jobOrderings.get(j).allele() == jobOrderings.get(jj).allele()) { + return false; + } else if (memoizedSucessors.get(jobs.get(j)).contains(jobs.get(jj)) && jobOrderings.get(j) + .allele() > jobOrderings.get(jj).allele()) { + return false; + } else if (memoizedSucessors.get(jobs.get(jj)).contains(jobs.get(j)) && jobOrderings.get(j) + .allele() < jobOrderings.get(jj).allele()) { + return false; + } + } + } + } + // var isValid = Arrays.stream(mappedJobs) + // .allMatch(j -> Arrays.stream(mappedJobs) + // .filter(jj -> j != jj) + // .allMatch(jj -> (jobOrderings.get(j) + // .allele() != jobOrderings.get(jj) + // .allele()) + // && + // (!memoizedSucessors.get(jobs.get(j)) + // .contains(jobs.get(jj)) + // || jobOrderings.get(j) + // .allele() < jobOrderings + // .get(jj) + // .allele()))); // !isSucessor(j, jj) or order(j) < order(jj) // if (!isValid) { // System.out.println(Arrays.stream(mappedJobs) @@ -105,7 +120,7 @@ public boolean test(Phenotype individual) { // .map(a -> "(%s, %s)".formatted(a.process(), a.instance())) // .reduce((a, b) -> a + ", " + b)); // } - return isValid; + return true; }); } diff --git a/rust-core/src/lib.rs b/rust-core/src/lib.rs index 0f451a1b..6fe33a71 100644 --- a/rust-core/src/lib.rs +++ b/rust-core/src/lib.rs @@ -51,7 +51,7 @@ pub trait DesignModel: Send + DowncastSync { let p = base_path.join(format!( "body_{}_{}_{}.{}", prefix_str, - h.category, + self.category(), suffix_str, self.extensions() .get(0) diff --git a/rust-orchestration/src/identification.rs b/rust-orchestration/src/identification.rs index ba0989cd..c63ba8ff 100644 --- a/rust-orchestration/src/identification.rs +++ b/rust-orchestration/src/identification.rs @@ -261,7 +261,6 @@ impl IdentificationModule for ExternalServerIdentificationModule { debug!("Recv error is: {}", err.to_string()); } } - {}; // self.write_line_to_input(format!("IDENTIFY {}", iteration).as_str()); // if let Ok(response) = self // .send_command( @@ -345,77 +344,65 @@ impl IdentificationModule for ExternalServerIdentificationModule { design_models: &Vec>, ) -> Vec> { // let mut integrated: Vec> = Vec::new(); - // save decision models and design models and ask the module to read them - for design_model in design_models { - // let message = DesignModelMessage::from_dyn_design_model(design_model.as_ref()); - // self.write_line_to_input(format!("DESIGN {}", message.to_json_str()).as_str()); - match self.send_design(design_model.as_ref()) { - Ok(a) => { - if !a.status().is_success() { - warn!( - "Module {} raised error at design model input: {}", - self.unique_identifier(), - a.text().unwrap_or("".to_string()) - ) - } - } - Err(_) => {} - }; + let mut form = reqwest::blocking::multipart::Form::new(); + for (i, design_model) in design_models.iter().enumerate() { + form = form.part( + format!("designModel{}", i), + reqwest::blocking::multipart::Part::text( + DesignModelMessage::from(design_model).to_json_str(), + ), + ); } - for decision_model in solved_decision_models { - // let message = DecisionModelMessage::from_dyn_decision_model(decision_model.as_ref()); - // self.write_line_to_input(format!("SOLVED INLINE {}", message.to_json_str()).as_str()); - match self.send_solved_decision(decision_model.as_ref()) { - Ok(a) => { - if !a.status().is_success() { + for (i, decision_model) in solved_decision_models.iter().enumerate() { + form = form.part( + format!("decisionModel{}", i), + reqwest::blocking::multipart::Part::text( + DecisionModelMessage::from(decision_model).to_json_str(), + ), + ); + } + match self + .get_client() + .post(format!( + "http://{}:{}/reverse", + self.get_address(), + self.get_port() + )) + .multipart(form) + .send() + .and_then(|x| x.text()) + { + Ok(response) => { + match serde_json::from_str::>(response.as_str()) { + Ok(v) => { + return v + .iter() + .map(|x| Arc::new(OpaqueDesignModel::from(x)) as Arc) + .collect(); + } + Err(e) => { warn!( - "Module {} raised error at solved model input: {}", + "Module {} produced an error at identification. Check it for correctness", + self.unique_identifier() + ); + debug!( + "Module {} error: {}", self.unique_identifier(), - a.text().unwrap_or("".to_string()) - ) + e.to_string() + ); + debug!("Response was: {}", response.as_str()); } } - Err(_) => {} - }; - } - if let Ok(response) = self - .send_command("integrate", &vec![]) - .and_then(|x| x.text()) - { - if let Ok(v) = serde_json::from_str::>(response.as_str()) { - return v - .iter() - .map(|x| Arc::new(OpaqueDesignModel::from(x)) as Arc) - .collect(); + } + Err(err) => { + warn!( + "Had an error while recovering identification results from module {}. Attempting to continue.", + self.unique_identifier() + ); + debug!("Recv error is: {}", err.to_string()); } } vec![] - // self.write_line_to_input("INTEGRATE"); - // self.map_output(|buf| { - // buf.lines() - // .flatten() - // .map(|line| { - // if line.contains("DESIGN") { - // let payload = &line[6..].trim(); - // if let Some(message) = DesignModelMessage::from_json_str(&payload) { - // let model = OpaqueDesignModel::from(message); - // let boxed = Arc::new(model) as Arc; - // return Some(boxed); - // }; - // } else if !line.trim().eq_ignore_ascii_case("FINISHED") { - // warn!( - // "Ignoring non-compliant integration result by module {}: {}", - // self.unique_identifier(), - // line - // ); - // } - // None - // }) - // .take_while(|x| x.is_some()) - // .flatten() - // .collect() - // }) - // .unwrap_or(Vec::new()) } } diff --git a/rust-orchestration/src/main.rs b/rust-orchestration/src/main.rs index 751839a3..8328ef9a 100644 --- a/rust-orchestration/src/main.rs +++ b/rust-orchestration/src/main.rs @@ -542,12 +542,11 @@ fn main() { } let solved_models: Vec> = dominant_sols.iter().map(|(x, _)| x.clone()).collect(); - if !dominant_sols.is_empty() { - info!("Starting integration"); + if !solved_models.is_empty() { + info!("Starting reverse identification"); let total_reversed: usize = imodules .par_iter() - .enumerate() - .map(|(_, imodule)| { + .map(|imodule| { let mut n_reversed = 0; for reverse in imodule.reverse_identification(&solved_models, &design_models) @@ -556,7 +555,7 @@ fn main() { reverse.write_to_dir( &reverse_path, format!("{}", n_reversed).as_str(), - "Orchestrator", + imodule.unique_identifier().as_str(), ); n_reversed += 1; debug!("Reverse identified a {} design model", reverse.category()); diff --git a/rust-orchestration/src/models.rs b/rust-orchestration/src/models.rs index b3785aa6..d0d33029 100644 --- a/rust-orchestration/src/models.rs +++ b/rust-orchestration/src/models.rs @@ -107,7 +107,7 @@ impl DesignModel for OpaqueDesignModel { } fn extensions(&self) -> Vec { - return self.extensions.to_owned(); + self.extensions.to_owned() } } diff --git a/scala-blueprints/src/main/scala/idesyde/blueprints/StandaloneIdentificationModule.scala b/scala-blueprints/src/main/scala/idesyde/blueprints/StandaloneIdentificationModule.scala index d5febf9f..c61801a8 100644 --- a/scala-blueprints/src/main/scala/idesyde/blueprints/StandaloneIdentificationModule.scala +++ b/scala-blueprints/src/main/scala/idesyde/blueprints/StandaloneIdentificationModule.scala @@ -606,14 +606,33 @@ trait StandaloneIdentificationModule } } ) - .get( - "/integrate", + .post( + "/reverse", ctx => { - val integrated = reverseIdentification( - solvedDecisionModels, - designModels - ) - ctx.result(write(integrated.map(DesignModelMessage.fromDesignModel(_)))) + if (ctx.isMultipartFormData()) { + var decisionModels = mutable.Set[DecisionModel](); + var designModels = mutable.Set[DesignModel](); + ctx + .formParamMap() + .forEach((name, entries) => { + if (name.startsWith("decisionModel")) { + entries.forEach(msg => { + decisionMessageToModel(DecisionModelMessage.fromJsonString(msg)) + .foreach(decisionModels.add) + }) + } else if (name.startsWith("designModel")) { + entries.forEach(msg => { + designMessageToModel(DesignModelMessage.fromJsonString(msg)) + .foreach(designModels.add) + }) + } + }); + var integrated = reverseIdentification(decisionModels.toSet, designModels.toSet); + ctx.result(write(integrated.map(DesignModelMessage.fromDesignModel(_)))) + } else { + ctx.status(500); + } + } ) .exception(