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sim_kajita_closed_loop.mdl.r2011a
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RTWCAPIRootIO off
GenerateASAP2 off
}
PropName "Components"
}
}
hdlcoderui.hdlcc {
$ObjectID 12
Version "1.11.0"
Description "HDL Coder custom configuration component"
Name "HDL Coder"
Array {
Type "Cell"
Dimension 1
Cell ""
PropName "HDLConfigFile"
}
HDLCActiveTab "0"
}
PropName "Components"
}
Name "Configuration"
CurrentDlgPage "Solver"
ConfigPrmDlgPosition [ 243, 69, 1123, 699 ]
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
BlockRotation 0
BlockMirror off
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
BlockParameterDefaults {
Block {
BlockType Clock
DisplayTime off
}
Block {
BlockType Constant
Value "1"
VectorParams1D on
SamplingMode "Sample based"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: Inherit from 'Constant value'"
LockScale off
SampleTime "inf"
FramePeriod "inf"
PreserveConstantTs off
}
Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParamMin "[]"
ParamMax "[]"
ParamDataTypeStr "Inherit: Same as input"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: Same as input"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Inport
Port "1"
OutputFunctionCall off
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchInputForFeedbackSignals off
Interpolate on
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
IgnoreLimit off
ZeroCross on
ContinuousStateAttributes "''"
}
Block {
BlockType MATLABFcn
MATLABFcn "sin"
OutputDimensions "-1"
OutputSignalType "auto"
Output1D on
SampleTime "-1"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: auto"
LockScale off
BusOutputAsStruct off
PortDimensions "-1"
VarSizeSig "Inherit"
SampleTime "-1"
SignalType "auto"
SamplingMode "auto"
SourceOfInitialOutputValue "Dialog"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
CheckFcnCallInpInsideContextMsg off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
DataTypeOverrideAppliesTo "AllNumericTypes"
MinMaxOverflowLogging "UseLocalSettings"
Variant off
GeneratePreprocessorConditionals off
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
CollapseMode "All dimensions"
CollapseDim "1"
InputSameDT on
AccumDataTypeStr "Inherit: Inherit via internal rule"
OutMin "[]"
OutMax "[]"
OutDataTypeStr "Inherit: Same as first input"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
NumInputs "1"
}
Block {
BlockType UnitDelay
X0 "0"
InputProcessing "Inherited"
SampleTime "1"
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
}
System {
Name "sim_kajita_closed_loop"
Location [2, 82, 1348, 715]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "125"
ReportName "simulink-default.rpt"
SIDHighWatermark "75"
Block {
BlockType ToWorkspace
Name "CoG"
SID "1"
Ports [1]
Position [765, 140, 825, 170]
BackgroundColor "red"
VariableName "CoG"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Structure With Time"
}
Block {
BlockType ToWorkspace
Name "CoG DDot2"
SID "71"
Ports [1]
Position [765, 270, 825, 300]
BackgroundColor "red"
VariableName "CoGDD"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Structure With Time"
}
Block {
BlockType ToWorkspace
Name "CoG Dot2"
SID "69"
Ports [1]
Position [765, 210, 825, 240]
BackgroundColor "red"
VariableName "CoGD"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Structure With Time"
}
Block {
BlockType Demux
Name "Demux"
SID "4"
Ports [1, 3]
Position [550, 129, 555, 211]
ShowName off
Outputs "3"
DisplayOption "bar"
}
Block {
BlockType Demux
Name "Demux1"
SID "47"
Ports [1, 3]
Position [550, 269, 555, 351]
ShowName off
Outputs "3"
DisplayOption "bar"
}
Block {
BlockType SubSystem
Name "Dynamic"
SID "5"
Ports [1, 2]
Position [325, 66, 420, 144]
BackgroundColor "cyan"
MinAlgLoopOccurrences off
PropExecContextOutsideSubsystem off
RTWSystemCode "Auto"
FunctionWithSeparateData off
Opaque off
RequestExecContextInheritance off
MaskHideContents off
System {
Name "Dynamic"
Location [196, 129, 1039, 487]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "125"
Block {
BlockType Inport
Name "U(t)"
SID "6"
Position [50, 163, 80, 177]
BackgroundColor "red"
IconDisplay "Port number"
}
Block {
BlockType Gain
Name "Gain"
SID "7"
Position [190, 215, 220, 245]
BackgroundColor "cyan"
Gain "Zc/g"
ParamDataTypeStr "Inherit: Inherit via internal rule"
OutDataTypeStr "Inherit: Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Integrator
Name "Integrator"
SID "8"
Ports [1, 1]
Position [110, 155, 140, 185]
BackgroundColor "cyan"
}
Block {
BlockType Integrator
Name "Integrator1"
SID "9"
Ports [1, 1]
Position [190, 155, 220, 185]
BackgroundColor "cyan"
InitialCondition "X0Dot"
}
Block {
BlockType Integrator
Name "Integrator2"
SID "10"
Ports [1, 1]
Position [255, 155, 285, 185]
BackgroundColor "cyan"
InitialCondition "X0"
}
Block {
BlockType Mux
Name "Mux"
SID "11"
Ports [3, 1]
Position [335, 14, 340, 96]
ShowName off
Inputs "3"
DisplayOption "bar"
}
Block {
BlockType Sum
Name "Sum"
SID "13"
Ports [2, 1]
Position [330, 160, 350, 180]
BackgroundColor "red"
ShowName off
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeStr "Inherit: Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Outport
Name "ZMPX"
SID "14"
Position [490, 163, 520, 177]
BackgroundColor "red"
IconDisplay "Port number"
}
Block {
BlockType Outport
Name "Z"
SID "15"
Position [490, 48, 520, 62]
BackgroundColor "red"
Port "2"
IconDisplay "Port number"
}
Line {
SrcBlock "U(t)"
SrcPort 1
DstBlock "Integrator"
DstPort 1
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "ZMPX"
DstPort 1
}
Line {
SrcBlock "Integrator"
SrcPort 1
Points [15, 0]
Branch {
DstBlock "Integrator1"
DstPort 1
}
Branch {
Points [0, 60]
DstBlock "Gain"