From 4eaca9794d8c083430558fc0048f8bf69b4bb2d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= Date: Mon, 19 Aug 2024 04:43:39 +0100 Subject: [PATCH] Solve naming conflict with Yosys Yosys and other synthesis tools already have internal ALU blocks which collide with a module named ALU --- src/main/scala/rocket/ALU.scala | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/main/scala/rocket/ALU.scala b/src/main/scala/rocket/ALU.scala index 20c2bdffeb3..5175977f36e 100644 --- a/src/main/scala/rocket/ALU.scala +++ b/src/main/scala/rocket/ALU.scala @@ -65,6 +65,8 @@ abstract class AbstractALU[T <: ALUFN](val aluFn: T)(implicit p: Parameters) ext } class ALU(implicit p: Parameters) extends AbstractALU(new ALUFN)(p) { + override def desiredName = "RocketALU" + // ADD, SUB val in2_inv = Mux(aluFn.isSub(io.fn), ~io.in2, io.in2) val in1_xor_in2 = io.in1 ^ in2_inv