DevMeeting - 2021-07-19/20

[jackkoenig]

Outreach

• [jiuyang] CCC Shanghai
  • Still Editing video.
  • Hopefully can finish up this week
• [jiuyang] None resolved Q&A
  • In chisel3 discussion, some user questions
  • 多维数组会导致IO的方向推断错误，这是不是一个bug?(Is it a bug that multidimensional arrays lead to incorrect inference of the direction of IO?) #2038
• [jiuyang] Send calendar invites on the mailing list?
  • Send ics link to GitHub Discussion.
  • Use mail to handle this, since ics depends on email.
  • Maybe google calendar?
  • Put the google calendar share to the github discussion
  • Jiuyang will do this

Updates

Pinned Items

• Priority PRs:
  • Module with multiple memories have no readmem statements firrtl#2168: Annoying issue where Dedup breaks some Verilog customization annotations
    • Fix memory annotation deduplication firrtl#2286** **merged
    • Fix memory annotation deduplication firrtl#2286 (comment) complains issue remains.
  • [jiuyang] Multi-dimension IO connection bug.
    • Reported in 多维数组会导致IO的方向推断错误，这是不是一个bug?(Is it a bug that multidimensional arrays lead to incorrect inference of the direction of IO?) #2038
      • Valid API bug?
      • [jiuyang] creates a bug issue and tracks it.

Discussion 1

• [chick] Identify specific memories to be implemented as SRAM cells ucb-art/rocket-dsp-utils#30
  • Rewrite vlsi_mem_gen into a Firrtl Transform firrtl#2202 might help.
    • Add another pass to alter DefAnnotatedMemory?
  • Add some concrete examples.
  • [kevin] Can we get a concrete example here?
• [adam] instance api

Discussion 2

• [chick] api-config-chipsalliance publishing
  • [jiuyang] I wanna do this, however, still need to talk to SiFive.
  • [jack] only question is what org we want it published under, will need a record on the chipsalliance.org DNS
• [jiuyang] Refactor CI and Tests, these PRs have dependencies.
  * Refactor tests #2004
  * [jack] Can you put this (and the other files being migrated into testing) in src/test/scala/chisel3/testers instead of in package chiselTests?
  * package name confliction
  * TestUtils does not seem to be a good user API.
  * [jack] cannot replicate the behavior of BasicTest unless we add stop.
  * IIRC chisel exposed stop in https://github.com/chipsalliance/chisel3/blob/master/core/src/main/scala/chisel3/Assert.scala#L80-L92
  * Speed up CI #2043
  * Really a speed up: from 30mins+ -> 8 mins
  * Jack reviewed:
  * [jack] Need to add an environment variable to replace if in GitHub Action.
  * See https://docs.github.com/en/actions/reference/environment-variables
• [jack] Example in README is not an average
  • https://github.com/chipsalliance/chisel3#what-does-chisel-code-look-like
  • https://gitter.im/freechipsproject/chisel3?at=60f4adc0ec10653d5a49fe18
  • Resolution: To keep consistent with following example, rename to “MovingSum3”
• [schuyler] Annotation Canonicalization (going beyond deduplication)
  • Ideas on what a generic solution would look like:
    • Define “metadata equality”
    • Canonicalize targets for “metadata equal” annotations
  • Fix memory annotation deduplication firrtl#2286
    • [jack] For the record, this was intended as a patch fix that might be generalizable, sort of a trial run
    • This pilots “Annotation deduplication”, but doesn’t handle more general “canonicalization”
  • May be possible to do automatically for at least SingleTargetAnnotations