From fe7dac3f1c6e2f6d89101c9582ebd207a2d1099e Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Wed, 15 Feb 2023 14:55:50 +0200 Subject: [PATCH 1/5] Update scripts to follow HDL main branch The following changes have been made: Add separate Jenkins file for hdl master branch Add VIVADOVERSION parameter Remove duplicates of HDL scripts: adi_project_xilinx.tcl adi_ip.tcl adi_project.tcl synth_designs.sh: Add root repo path Replace "master" with "main" for HDL repo --- CI/gen_doc/Makefile | 8 +- CI/gen_doc/docs/_pages/targeting.md | 2 +- CI/scripts/Makefile | 8 +- CI/scripts/adi_ip.tcl | 387 ----------- CI/scripts/adi_project.tcl | 205 ------ CI/scripts/adi_project_xilinx.tcl | 604 ------------------ CI/scripts/build_bsp.sh | 1 - CI/scripts/dockermake | 2 +- CI/scripts/synth_designs.sh | 14 +- CI/scripts/system_project_rxtx.tcl | 5 +- Jenkinsfile | 3 +- JenkinsfileCron | 1 + Jenkinsfile_dev | 110 ++++ .../AnalogDevices/+AnalogDevices/plugin_rd.m | 3 +- test/adi_build.tcl | 27 +- 15 files changed, 152 insertions(+), 1228 deletions(-) delete mode 100644 CI/scripts/adi_ip.tcl delete mode 100644 CI/scripts/adi_project.tcl delete mode 100644 CI/scripts/adi_project_xilinx.tcl create mode 100644 Jenkinsfile_dev diff --git a/CI/gen_doc/Makefile b/CI/gen_doc/Makefile index f1013b0a..dd6b1af3 100644 --- a/CI/gen_doc/Makefile +++ b/CI/gen_doc/Makefile @@ -1,7 +1,7 @@ # Usage: -# make MLRELEASE= HDLBRANCH= +# make MLRELEASE= HDLBRANCH= # Example -# make build MLRELEASE=R2018b HDLBRANCH=hdl_2018_r1 +# make build MLRELEASE=R2022b HDLBRANCH=hdl_2021_r1 SHELL := /bin/bash @@ -11,6 +11,10 @@ ifeq ($(MLRELEASE),) MLRELEASE := R2021a endif +ifeq ($(VIVADORELEASE),) +VIVADORELEASE := 2022.2 +endif + ifeq ($(HDLBRANCH),) HDLBRANCH := hdl_2018_r2 endif diff --git a/CI/gen_doc/docs/_pages/targeting.md b/CI/gen_doc/docs/_pages/targeting.md index 8e3834ab..d6016a92 100644 --- a/CI/gen_doc/docs/_pages/targeting.md +++ b/CI/gen_doc/docs/_pages/targeting.md @@ -11,7 +11,7 @@ High-Speed Converter Toolbox supports the IP Core generation flow from MathWorks ## Getting Started -To perform targeting will require FPGA vendor tools for the FPGA system. For Xilinx this will be Vivado and the toolbox will require specific versions for each release. For the current release this is Vivado 2022.2. Using other versions are not supported. To build the necessary BOOT.BIN files will require the Xilinx SDK as well. +To perform targeting will require FPGA vendor tools for the FPGA system. For Xilinx this will be Vivado and the toolbox will require specific versions for each release. For the current release this is Vivado 2022.2. Using other versions are not supported. To build the necessary BOOT.BIN files will require the Xilinx Vitis as well. Once you have the installed the necessary 3rd party tools MATLAB needs to be told where they are installed by use of the [hdlsetuptoolpath](https://www.mathworks.com/help/hdlcoder/ref/hdlsetuptoolpath.html) command. For Windows the following MATLAB command can be used: diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile index 38519d88..75bcc4e4 100644 --- a/CI/scripts/Makefile +++ b/CI/scripts/Makefile @@ -1,7 +1,7 @@ # Usage: -# make MLRELEASE= HDLBRANCH= +# make MLRELEASE= HDLBRANCH= # Example -# make build MLRELEASE=R2018b HDLBRANCH=hdl_2018_r1 +# make build MLRELEASE=R2022b HDLBRANCH=hdl_2021_r2 SHELL := /bin/bash @@ -11,6 +11,10 @@ ifeq ($(MLRELEASE),) MLRELEASE := R2023b endif +ifeq ($(VIVADORELEASE),) +VIVADORELEASE := 2022.2 +endif + ifeq ($(HDLBRANCH),) HDLBRANCH := hdl_2022_r2 endif diff --git a/CI/scripts/adi_ip.tcl b/CI/scripts/adi_ip.tcl deleted file mode 100644 index 2ccd9b15..00000000 --- a/CI/scripts/adi_ip.tcl +++ /dev/null @@ -1,387 +0,0 @@ -## ############################################################################################### -## ############################################################################################### -## check tool version - -if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2018.2" -} - -if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { - set IGNORE_VERSION_CHECK 1 -} elseif {![info exists IGNORE_VERSION_CHECK]} { - set IGNORE_VERSION_CHECK 0 -} - -## ############################################################################################### -## ############################################################################################### -## ip related stuff - -proc adi_ip_ttcl {ip_name ip_constr_files} { - - set cdir [pwd] - set m_file "" - set ip_constr_files_clean "" - foreach m_file $ip_constr_files { - file copy -force $m_file $cdir - set m_file [file tail $m_file] - lappend ip_constr_files_clean $m_file - } - set ip_constr_files $ip_constr_files_clean - - set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] - set f [ipx::add_file $ip_constr_files $proj_filegroup] - set_property -dict [list \ - type ttcl \ - ] $f - ipx::reorder_files -front $ip_constr_files $proj_filegroup -} - -# add ttcl file to the simulation file set -proc adi_ip_sim_ttcl {ip_name ip_files} { - - set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] - set f [ipx::add_file $ip_files $proj_filegroup] - set_property -dict [list \ - type ttcl \ - ] $f - ipx::reorder_files -front $ip_files $proj_filegroup -} - -proc adi_ip_bd {ip_name ip_bd_files} { - set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] - if {$proj_filegroup == {}} { - set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] - } - set f [ipx::add_file $ip_bd_files $proj_filegroup] - set_property -dict [list \ - type tclSource \ - ] $f -} - -proc adi_ip_infer_streaming_interfaces {ip_name} { - - ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] - -} - -proc adi_ip_infer_mm_interfaces {ip_name} { - - ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - -} - -proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { - foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { - set_property ENABLEMENT_DEPENDENCY $dependency $port - if {$driver_value != {}} { - set_property DRIVER_VALUE $driver_value $port - } - } -} - -proc adi_set_bus_dependency {bus prefix dependency} { - set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] - adi_set_ports_dependency $prefix $dependency 0 -} - -proc adi_add_port_map {bus phys logic} { - set map [ipx::add_port_map $phys $bus] - set_property "PHYSICAL_NAME" $phys $map - set_property "LOGICAL_NAME" $logic $map -} - -proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { - set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] - - set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus - set_property "BUS_TYPE_VLNV" $bus_type $bus - set_property "INTERFACE_MODE" $mode $bus - - foreach port_map $port_maps { - adi_add_port_map $bus {*}$port_map - } -} - -proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { - for {set i 0} {$i < 8} {incr i} { - set bus_name [format "%s%d" $bus_name_prefix $i] - set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] - - set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus - set_property "BUS_TYPE_VLNV" $bus_type $bus - set_property "INTERFACE_MODE" $mode $bus - - if {$dependency ne ""} { - set bus_dependency [string map [list "{i}" $i] $dependency] - set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus - } - - foreach port_map $port_maps { - lassign $port_map phys logic width - set map [ipx::add_port_map $phys $bus] - set_property "PHYSICAL_NAME" $phys $map - set_property "LOGICAL_NAME" $logic $map - set_property "PHYSICAL_RIGHT" [expr $i*$width] $map - set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map - } - } -} - -proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { - set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] - set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] - set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf - set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf - set_property display_name $clock_inf_name $clock_inf - set clock_map [ipx::add_port_map "CLK" $clock_inf] - set_property physical_name $clock_signal_name $clock_map - - set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] - set_property value $bus_inf_name $assoc_busif - - if { $reset_signal_name != "" } { - set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] - set_property value $reset_signal_name $assoc_reset - - set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] - set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] - set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf - set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf - set_property display_name $reset_inf_name $reset_inf - set_property interface_mode $reset_signal_mode $reset_inf - set reset_map [ipx::add_port_map "RST" $reset_inf] - set_property physical_name $reset_signal_name $reset_map - - set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] - if {[string match {*[Nn]} $reset_signal_name] == 1} { - set_property value "ACTIVE_LOW" $reset_polarity - } else { - set_property value "ACTIVE_HIGH" $reset_polarity - } - } -} - -proc adi_ip_add_core_dependencies {vlnvs} { - foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { - foreach vlnv $vlnvs { - ipx::add_subcore $vlnv $file_group - } - } -} - -## ############################################################################################### -## ############################################################################################### -## ip related stuff - -variable ip_constr_files - -proc adi_ip_create {ip_name} { - - global ad_hdl_dir - global ad_phdl_dir - global ip_constr_files - global REQUIRED_VIVADO_VERSION - global IGNORE_VERSION_CHECK - - set VIVADO_VERSION [version -short] - if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { - puts -nonewline "CRITICAL WARNING: vivado version mismatch; " - puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " - puts -nonewline "got $VIVADO_VERSION.\n" - } - - create_project $ip_name . -force - - ## Load custom message severity definitions - source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl - - set ip_constr_files "" - set lib_dirs $ad_hdl_dir/library - if {$ad_hdl_dir ne $ad_phdl_dir} { - lappend lib_dirs $ad_phdl_dir/library - } - - set_property ip_repo_paths $lib_dirs [current_fileset] - update_ip_catalog -} - -proc adi_ip_files {ip_name ip_files} { - - global ip_constr_files - - set cdir [pwd] - set ip_constr_files "" - set ip_files_clean "" - foreach m_file $ip_files { - file copy -force $m_file $cdir - set m_file [file tail $m_file] - puts $m_file - if {[file extension $m_file] eq ".xdc"} { - lappend ip_constr_files $m_file - } - lappend ip_files_clean $m_file - } - - set ip_files $ip_files_clean - - set proj_fileset [get_filesets sources_1] - add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files - add_files -norecurse -copy_to $cdir -force -fileset $proj_fileset $ip_files - set_property "top" "$ip_name" $proj_fileset -} - -proc adi_ip_properties_lite {ip_name} { - - global ip_constr_files - - ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices - set_property name $ip_name [ipx::current_core] - set_property vendor_display_name {Analog Devices} [ipx::current_core] - set_property company_url {http://www.analog.com} [ipx::current_core] - - set i_families "" - foreach i_part [get_parts] { - lappend i_families [get_property FAMILY $i_part] - } - set i_families [lsort -unique $i_families] - set s_families [get_property supported_families [ipx::current_core]] - foreach i_family $i_families { - set s_families "$s_families $i_family Production" - set s_families "$s_families $i_family Beta" - } - set_property supported_families $s_families [ipx::current_core] - ipx::save_core - - ipx::remove_all_bus_interface [ipx::current_core] - set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] - foreach map $memory_maps { - ipx::remove_memory_map [lindex $map 2] [ipx::current_core ] - } - ipx::save_core - - set i_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] - foreach i_file $ip_constr_files { - set i_module [file tail $i_file] - regsub {_constr\.xdc} $i_module {} i_module - ipx::add_file $i_file $i_filegroup - ipx::reorder_files -front $i_file $i_filegroup - set_property SCOPED_TO_REF $i_module [ipx::get_files $i_file -of_objects $i_filegroup] - } - ipx::save_core -} - -proc adi_ip_properties {ip_name} { - - adi_ip_properties_lite $ip_name - - ipx::infer_bus_interface {\ - s_axi_awvalid \ - s_axi_awaddr \ - s_axi_awprot \ - s_axi_awready \ - s_axi_wvalid \ - s_axi_wdata \ - s_axi_wstrb \ - s_axi_wready \ - s_axi_bvalid \ - s_axi_bresp \ - s_axi_bready \ - s_axi_arvalid \ - s_axi_araddr \ - s_axi_arprot \ - s_axi_arready \ - s_axi_rvalid \ - s_axi_rdata \ - s_axi_rresp \ - s_axi_rready} \ - xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] - - ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] - ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] - - set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] - set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] - - if {$raddr_width != $waddr_width} { - puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] - set range 65536 - } else { - if {$raddr_width >= 16} { - set range 65536 - } else { - set range [expr 1 << $raddr_width] - } - } - - ipx::add_memory_map {s_axi} [ipx::current_core] - set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] - ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] - set_property range $range [ipx::get_address_blocks axi_lite \ - -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] - ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] - ipx::save_core -} - -## ############################################################################################### -## ############################################################################################### -## interface related stuff - -proc adi_if_define {name} { - - ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 - ipx::create_bus_definition analog.com interface $name 1.0 - - set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] - set_property xml_file_name ${name}.xml [ipx::current_busdef] - set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] - - ipx::save_abstraction_definition [ipx::current_busabs] - ipx::save_bus_definition [ipx::current_busdef] -} - -proc adi_if_ports {dir width name {type none}} { - - ipx::add_bus_abstraction_port $name [ipx::current_busabs] - set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] - set_property master_presence required $m_intf - set_property slave_presence required $m_intf - set_property master_width $width $m_intf - set_property slave_width $width $m_intf - - set m_dir "in" - set s_dir "out" - if {$dir eq "output"} { - set m_dir "out" - set s_dir "in" - } - - set_property master_direction $m_dir $m_intf - set_property slave_direction $s_dir $m_intf - - if {$type ne "none"} { - set_property is_${type} true $m_intf - } - - ipx::save_bus_definition [ipx::current_busdef] - ipx::save_abstraction_definition [ipx::current_busabs] -} - -proc adi_if_infer_bus {if_name mode name maps} { - - ipx::add_bus_interface $name [ipx::current_core] - set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] - set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if - set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if - set_property interface_mode $mode $m_bus_if - - foreach map $maps { - set m_maps [regexp -all -inline {\S+} $map] - lassign $m_maps p_name p_map - ipx::add_port_map $p_name $m_bus_if - set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] - } -} - -## ############################################################################################### -## ############################################################################################### diff --git a/CI/scripts/adi_project.tcl b/CI/scripts/adi_project.tcl deleted file mode 100644 index f777ff29..00000000 --- a/CI/scripts/adi_project.tcl +++ /dev/null @@ -1,205 +0,0 @@ - -variable p_board -variable p_device -variable sys_zynq -variable p_prcfg_init -variable p_prcfg_list -variable p_prcfg_status - -if {![info exists REQUIRED_VIVADO_VERSION]} { - set REQUIRED_VIVADO_VERSION "2018.2" -} - -if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { - set IGNORE_VERSION_CHECK 1 -} elseif {![info exists IGNORE_VERSION_CHECK]} { - set IGNORE_VERSION_CHECK 0 -} - -set p_board "not-applicable" -set p_device "none" -set sys_zynq 1 -set ADI_POWER_OPTIMIZATION 0 - -proc adi_project_xilinx {project_name project_dir update_tcl {mode 0}} { - - global ad_hdl_dir - global ad_phdl_dir - global p_board - global p_device - global sys_zynq - global REQUIRED_VIVADO_VERSION - global IGNORE_VERSION_CHECK - - if [regexp "_ac701$" $project_name] { - set p_device "xc7a200tfbg676-2" - set p_board "xilinx.com:ac701:part0:1.0" - set sys_zynq 0 - } - if [regexp "_kc705$" $project_name] { - set p_device "xc7k325tffg900-2" - set p_board "xilinx.com:kc705:part0:1.1" - set sys_zynq 0 - } - if [regexp "_vc707$" $project_name] { - set p_device "xc7vx485tffg1761-2" - set p_board "xilinx.com:vc707:part0:1.1" - set sys_zynq 0 - } - if [regexp "_kcu105$" $project_name] { - set p_device "xcku040-ffva1156-2-e" - set p_board "xilinx.com:kcu105:part0:1.1" - set sys_zynq 0 - } - if [regexp "_zed$" $project_name] { - set p_device "xc7z020clg484-1" - set p_board "em.avnet.com:zed:part0:1.3" - set sys_zynq 1 - } - if [regexp "_microzed$" $project_name] { - set p_device "xc7z010clg400-1" - set p_board "not-applicable" - set sys_zynq 1 - } - if [regexp "_zc702$" $project_name] { - set p_device "xc7z020clg484-1" - set p_board "xilinx.com:zc702:part0:1.2" - set sys_zynq 1 - } - if [regexp "_zc706$" $project_name] { - set p_device "xc7z045ffg900-2" - set p_board "xilinx.com:zc706:part0:1.2" - set sys_zynq 1 - } - if [regexp "_mitx045$" $project_name] { - set p_device "xc7z045ffg900-2" - set p_board "not-applicable" - set sys_zynq 1 - } - if [regexp "_zcu102$" $project_name] { - set p_device "xczu9eg-ffvb1156-2-e" - set p_board "xilinx.com:zcu102:part0:3.1" - set sys_zynq 2 - } - - #Added - set project_name_org $project_name - set project_name vivado_prj - - set VIVADO_VERSION [version -short] - if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} { - puts -nonewline "CRITICAL WARNING: vivado version mismatch; " - puts -nonewline "expected $REQUIRED_VIVADO_VERSION, " - puts -nonewline "got $VIVADO_VERSION.\n" - } - - #Added - adi_setup_libs - - if {$mode == 0} { - set project_system_dir "./$project_name.srcs/sources_1/bd/system" - #Removed - #create_project $project_name . -part $p_device -force - } else { - set project_system_dir ".srcs/sources_1/bd/system" - #Removed - #create_project -in_memory -part $p_device - } - - if {$mode == 1} { - file mkdir $project_name.data - } - - if {$p_board ne "not-applicable"} { - set_property board_part $p_board [current_project] - } - - #Removed - #set lib_dirs $ad_hdl_dir/library - #if {$ad_hdl_dir ne $ad_phdl_dir} { - # lappend lib_dirs $ad_phdl_dir/library - #} - - #set_property ip_repo_paths $lib_dirs [current_fileset] - #update_ip_catalog - - set_msg_config -id {BD 41-1348} -new_severity info - set_msg_config -id {BD 41-1343} -new_severity info - set_msg_config -id {BD 41-1306} -new_severity info - set_msg_config -id {IP_Flow 19-1687} -new_severity info - set_msg_config -id {filemgmt 20-1763} -new_severity info - set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity error - - #Added - create_bd_design "system" - source $project_dir/system_bd.tcl - if {$project_name_org != "adrv9361z7035_ccbox_lvds_modem"} { - source $project_dir/$update_tcl - } - - - regenerate_bd_layout - save_bd_design - validate_bd_design - - set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd] - generate_target {synthesis implementation} [get_files $project_system_dir/system.bd] - make_wrapper -files [get_files $project_system_dir/system.bd] -top - - if {$mode == 0} { - import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v - } else { - write_hwdef -file "$project_name.data/$project_name.hwdef" - } -} - -#Added -proc adi_setup_libs {} { - global ad_hdl_dir - global ad_phdl_dir - - set lib_dirs [get_property ip_repo_paths [current_fileset]] - - lappend lib_dirs $ad_hdl_dir/library - if {$ad_hdl_dir ne $ad_phdl_dir} { - lappend lib_dirs $ad_phdl_dir/library - } - - set_property ip_repo_paths $lib_dirs [current_fileset] - update_ip_catalog - adi_add_archive_ip $lib_dirs -} - -#Added -proc adi_add_archive_ip {lib_dirs} { - global ad_hdl_dir - global ad_phdl_dir - foreach libDir $lib_dirs { - set ipList [glob -nocomplain -directory $libDir *.zip] - foreach ipCore $ipList { - catch {update_ip_catalog -add_ip $ipCore -repo_path $libDir} - file delete -force $ipCore - } - } -} - -proc adi_project_files {project_name project_files} { - - global ad_hdl_dir - global ad_phdl_dir - global proj_dir - - #Added - cd $proj_dir - - add_files -norecurse -fileset sources_1 $project_files - set_property top system_top [current_fileset] - - #Added - cd $ad_hdl_dir -} - -proc adi_project_run {project_name} { - #Removed -} - diff --git a/CI/scripts/adi_project_xilinx.tcl b/CI/scripts/adi_project_xilinx.tcl deleted file mode 100644 index aafb697b..00000000 --- a/CI/scripts/adi_project_xilinx.tcl +++ /dev/null @@ -1,604 +0,0 @@ -## Define the ADI_USE_OOC_SYNTHESIS environment variable to enable out of context -# synthesis -if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} { - if {[string equal $::env(ADI_USE_OOC_SYNTHESIS) n]} { - set ADI_USE_OOC_SYNTHESIS 0 - } else { - set ADI_USE_OOC_SYNTHESIS 1 - } -} elseif {![info exists ADI_USE_OOC_SYNTHESIS]} { - set ADI_USE_OOC_SYNTHESIS 1 -} - -## Set number of parallel out of context jobs through environment variable -if {![info exists ::env(ADI_MAX_OOC_JOBS)]} { - set ADI_MAX_OOC_JOBS 4 -} else { - set ADI_MAX_OOC_JOBS $::env(ADI_MAX_OOC_JOBS) -} - -## Set to enable incremental compilation -set ADI_USE_INCR_COMP 1 - -## Set to enable power optimization -set ADI_POWER_OPTIMIZATION 0 - -## Initialize global variables -set p_board "not-applicable" -set p_device "none" -set sys_zynq 1 - -set p_prcfg_init "" -set p_prcfg_list "" -set p_prcfg_status "" - -## Creates a Xilinx project for a given board -# -# \param[project_name] - name of the project -# \param[mode] - if set non-project mode will be used, otherwise project mode -# flow, see UG892 for more information -# \param[parameter_list] - a list of global parameters (parameters of the -# system_top module) -# -# Supported carrier names are: ac701, kc705, vc707, vcu118, vcu128, kcu105, zed, -# microzed, zc702, zc706, mitx405, zcu102. -# -proc adi_project {project_name {mode 0} {parameter_list {}} } { - - set device "" - set board "" - - # Determine the device based on the board name - if [regexp "_ac701$" $project_name] { - set device "xc7a200tfbg676-2" - set board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end] - } - if [regexp "_kc705$" $project_name] { - set device "xc7k325tffg900-2" - set board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end] - } - if [regexp "_vc707$" $project_name] { - set device "xc7vx485tffg1761-2" - set board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end] - } - if [regexp "_vcu118$" $project_name] { - set device "xcvu9p-flga2104-2L-e" - set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end] - } - if [regexp "_vcu128$" $project_name] { - set device "xcvu37p-fsvh2892-2L-e" - set board [lindex [lsearch -all -inline [get_board_parts] *vcu128:part0*] end] - } - if [regexp "_kcu105$" $project_name] { - set device "xcku040-ffva1156-2-e" - set board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end] - } - if [regexp "_zed$" $project_name] { - set device "xc7z020clg484-1" - set board [lindex [lsearch -all -inline [get_board_parts] *zed*] end] - } - if [regexp "_coraz7s$" $project_name] { - set device "xc7z007sclg400-1" - set board "not-applicable" - } - if [regexp "_microzed$" $project_name] { - set device "xc7z010clg400-1" - set board "not-applicable" - } - if [regexp "_zc702$" $project_name] { - set device "xc7z020clg484-1" - set board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end] - } - if [regexp "_zc706$" $project_name] { - set device "xc7z045ffg900-2" - set board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end] - } - if [regexp "_mitx045$" $project_name] { - set device "xc7z045ffg900-2" - set board "not-applicable" - } - if [regexp "_zcu102$" $project_name] { - set device "xczu9eg-ffvb1156-2-e" - set board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end] - } - if [regexp "_vmk180_es1$" $project_name] { - enable_beta_device xcvm* - xhub::refresh_catalog [xhub::get_xstores xilinx_board_store] - xhub::install [xhub::get_xitems xilinx.com:xilinx_board_store:vmk180_es:*] -quiet - set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] - set device "xcvm1802-vsva2197-2MP-e-S-es1" - set board [lindex [lsearch -all -inline [get_board_parts] *vmk180_es*] end] - } - if [regexp "_vmk180$" $project_name] { - set device "xcvm1802-vsva2197-2MP-e-S" - set board [lindex [lsearch -all -inline [get_board_parts] *vmk180*] end] - } - if [regexp "_vck190$" $project_name] { - set device "xcvc1902-vsva2197-2MP-e-S" - set board [lindex [lsearch -all -inline [get_board_parts] *vck190*] end] - } - if [regexp "_vc709$" $project_name] { - set device "xc7vx690tffg1761-2" - set board [lindex [lsearch -all -inline [get_board_parts] *vc709*] end] - } - - adi_project_create $project_name $mode $parameter_list $device $board -} - - -## Creates a Xilinx project. -# -# \param[project_name] - name of the project -# \param[mode] - if set non-project mode will be used, otherwise project mode -# flow, see UG892 for more information -# \param[parameter_list] - a list of global parameters (parameters of the -# system_top module) -# \param[device] - Canonical Xilinx device string -# \param[board] - board BSP name (optional) -# -proc adi_project_create {project_name mode parameter_list device {board "not-applicable"}} { - - global ad_hdl_dir - global ad_ghdl_dir - global p_board - global p_device - global sys_zynq - global required_vivado_version - global IGNORE_VERSION_CHECK - global ADI_USE_OOC_SYNTHESIS - global ADI_USE_INCR_COMP - - ## update the value of $p_device only if it was not already updated elsewhere - if {$p_device eq "none"} { - set p_device $device - } - set p_board $board - - if [regexp "^xc7z" $p_device] { - set sys_zynq 1 - } elseif [regexp "^xczu" $p_device] { - set sys_zynq 2 - } elseif [regexp "^xcv\[ecmph\]" $p_device] { - set sys_zynq 3 - } else { - set sys_zynq 0 - } - - set VIVADO_VERSION [version -short] - if {$IGNORE_VERSION_CHECK} { - if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} { - puts -nonewline "CRITICAL WARNING: vivado version mismatch; " - puts -nonewline "expected $required_vivado_version, " - puts -nonewline "got $VIVADO_VERSION.\n" - } - } else { - if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} { - puts -nonewline "ERROR: vivado version mismatch; " - puts -nonewline "expected $required_vivado_version, " - puts -nonewline "got $VIVADO_VERSION.\n" - puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" - exit 2 - } - } - - if {[info exists ::env(MATLAB)]} { - set MATLAB 1 - set project_name "vivado_prj" - set project_root $ad_hdl_dir - if {$mode != 0} { - puts -nonewline "MATLAB builds do not support mode 2" - exit 2 - } - } else { - set MATLAB 0 - set project_root [pwd] - } - - if {$mode == 0} { - set project_system_dir "$project_root/$project_name.srcs/sources_1/bd/system" - if {$MATLAB == 0} { - create_project $project_name . -part $p_device -force - } - } else { - set project_system_dir "$project_root/.srcs/sources_1/bd/system" - create_project -in_memory -part $p_device - } - - if {$mode == 1} { - file mkdir $project_root/$project_name.data - } - - if {$p_board ne "not-applicable"} { - set_property board_part $p_board [current_project] - } - - if {$MATLAB == 0} { - set lib_dirs $ad_hdl_dir/library - } else { - set lib_dirs [get_property ip_repo_paths [current_fileset]] - lappend lib_dirs $ad_hdl_dir/library - } - if {[info exists ::env(ADI_GHDL_DIR)]} { - if {$ad_hdl_dir ne $ad_ghdl_dir} { - lappend lib_dirs $ad_ghdl_dir/library - } - } else { - # puts -nonew-line "INFO: ADI_GHDL_DIR not defined.\n" - } - - # Set a common IP cache for all projects - if {$ADI_USE_OOC_SYNTHESIS == 1} { - if {[file exists $ad_hdl_dir/ipcache] == 0} { - file mkdir $ad_hdl_dir/ipcache - } - config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache - } - - set_property ip_repo_paths $lib_dirs [current_fileset] - update_ip_catalog - - ## Load custom message severity definitions - - if {![info exists ::env(ADI_DISABLE_MESSAGE_SUPPRESION)]} { - source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl - } - - ## In Vivado there is a limit for the number of warnings and errors which are - ## displayed by the tool for a particular error or warning; the default value - ## of this limit is 100. - ## Overrides the default limit to 2000. - set_param messaging.defaultLimit 2000 - - # Set parameters of the top level file - # Make the same parameters available to system_bd.tcl - set proj_params [get_property generic [current_fileset]] - foreach {param value} $parameter_list { - lappend proj_params $param=$value - set ad_project_params($param) $value - } - set_property generic $proj_params [current_fileset] - - create_bd_design "system" - source system_bd.tcl - - save_bd_design - validate_bd_design - - if {$ADI_USE_OOC_SYNTHESIS == 1} { - set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd] - } else { - set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd] - } - generate_target {synthesis implementation} [get_files $project_system_dir/system.bd] - if {$ADI_USE_OOC_SYNTHESIS == 1} { - export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet - create_ip_run [get_files $project_system_dir/system.bd] - } - make_wrapper -files [get_files $project_system_dir/system.bd] -top - - if {$mode == 0} { - import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v - } else { - write_hwdef -file "$project_name.data/$project_name.hwdef" - } - - if {$ADI_USE_INCR_COMP == 1} { - if {[file exists ./reference.dcp]} { - set_property incremental_checkpoint ./reference.dcp [get_runs impl_1] - } - } - -} - -## Add source files to an exiting project. -# -# \param[project_name] - name of the project -# \param[project_files] - list of project files -# -proc adi_project_files {project_name project_files} { - - foreach pfile $project_files { - if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} { - add_files -norecurse -fileset constrs_1 $pfile - } elseif [regexp "_constr.tcl" $pfile] { - add_files -norecurse -fileset sources_1 $pfile - } else { - add_files -norecurse -fileset sources_1 $pfile - } - } - - # NOTE: top file name is always system_top - set_property top system_top [current_fileset] -} - -## Run an existing project (generate bit stream). -# -# \param[project_name] - name of the project -# -proc adi_project_run {project_name} { - - global ADI_POWER_OPTIMIZATION - global ADI_USE_OOC_SYNTHESIS - global ADI_MAX_OOC_JOBS - - if {[info exists ::env(SKIP_SYNTHESIS)]} { - puts "Skipping synthesis" - return - } - - if {$ADI_USE_OOC_SYNTHESIS == 1} { - launch_runs -jobs $ADI_MAX_OOC_JOBS system_*_synth_1 synth_1 - } else { - launch_runs synth_1 - } - wait_on_run synth_1 - open_run synth_1 - report_timing_summary -file timing_synth.log - - if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} { - set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] - } - - if {$ADI_POWER_OPTIMIZATION == 1} { - set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] - set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] - } - - set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]] - - launch_runs impl_1 -to_step write_bitstream - wait_on_run impl_1 - open_run impl_1 - report_timing_summary -warn_on_violation -file timing_impl.log - - if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} { - set csv_file resource_utilization.csv - if {[ catch { - xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet - set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]] - set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]] - set worst_slack_setup [get_property SLACK [get_timing_paths -setup]] - set worst_slack_hold [get_property SLACK [get_timing_paths -hold]] - - set fileRead [open $csv_file r] - set lines [split [read $fileRead] "\n"] - set names_line [lindex $lines end-3] - set values_line [lindex $lines end-2] - close $fileRead - - set fileWrite [open $csv_file w] - puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack" - puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold" - close $fileWrite - } issue ] != 0 } { - puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed" - } - - # Define a list of IPs for which to generate report utilization - set IP_list { - ad_ip_jesd_204_tpl_adc - ad_ip_jesd_204_tpl_dac - axi_jesd204_rx - axi_jesd204_tx - jesd204_rx - jesd204_tx - axi_adxcvr - util_adxcvr - axi_dmac - util_cpack2 - util_upack2 - } - - foreach IP_name $IP_list { - set output_file ${IP_name}_resource_utilization.log - file delete $output_file - foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] { - report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet - report_property $IP_instance -file $output_file -append -quiet - set report_file [ open $output_file a ] - puts $report_file "\n\n\n" - close $report_file - } - } - } else { - puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set" - } - - if {[info exists ::env(ADI_GENERATE_XPA)]} { - set csv_file power_analysis.csv - set Layers "8to11" - set CapLoad "20" - set ToggleRate "15.00000" - set StatProb "0.500000" - - set_load $CapLoad [all_outputs] - set_operating_conditions -board_layers $Layers - set_switching_activity -default_toggle_rate $ToggleRate - set_switching_activity -default_static_probability $StatProb - set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all - set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all - report_power -file $csv_file - - set fileRead [open $csv_file r] - set filecontent [read $fileRead] - set input_list [split $filecontent "\n"] - - set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"] - set on_chip_pwr "[lindex [lindex $TextList 0] 6] W" - set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"] - set junction_temp "[lindex [lindex $TextList 0] 5] *C" - close $fileRead - - set fileWrite [open $csv_file w] - puts $fileWrite "On-chip_power,Junction_temp" - puts $fileWrite "$on_chip_pwr,$junction_temp" - close $fileWrite - } else { - puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set" - } - - # Look for undefined clocks which do not show up in the timing summary - set timing_check [check_timing -override_defaults no_clock -no_header -return_string] - if {[regexp { (\d+) register} $timing_check -> num_regs]} { - - if {[info exist num_regs]} { - if {$num_regs > 0} { - puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details." - check_timing -override_defaults no_clock -verbose -file no_clock.log - } - } - - } else { - puts "CRITICAL WARNING: The search for undefined clocks failed !!!" - } - - file mkdir $project_name.sdk - - set timing_string $[report_timing_summary -return_string] - if { [string match "*VIOLATED*" $timing_string] == 1 || - [string match "*Timing constraints are not met*" $timing_string] == 1} { - write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top_bad_timing.xsa - return -code error [format "ERROR: Timing Constraints NOT met!"] - } else { - write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top.xsa - } -} - -## Run synthesis on an partial design; use it in Partial Reconfiguration flow. -# -# \param[project_name] - project name -# \param[prcfg_name] - name of the partial design -# \param[hdl_files] - hdl source of the partial design -# \param[xdc_files] - XDC constraint source of the partial design -# -proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} { - - global p_device - - set p_prefix "$project_name.data/$project_name" - - if {$prcfg_name eq ""} { - - read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v - read_verilog $hdl_files - read_xdc $xdc_files - - synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds - write_checkpoint -force $p_prefix.synth.dcp - close_project - - } else { - - create_project -in_memory -part $p_device - read_verilog $hdl_files - synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds - write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp - close_project - } -} - -## Run implementation on an partial design; use it in Partial Reconfiguration -# flow. -# -# \param[project_name] - project name -# \param[prcfg_name] - name of the partial design -# \param[xdc_files] - XDC constraint source of the partial design -# -proc adi_project_impl {project_name prcfg_name {xdc_files ""}} { - - global p_device - global p_prcfg_init - global p_prcfg_list - global p_prcfg_status - - set p_prefix "$project_name.data/$project_name" - - if {$prcfg_name eq "default"} { - set p_prcfg_status 0 - set p_prcfg_list "" - set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp" - file mkdir $project_name.sdk - } - - if {$prcfg_name eq "default"} { - - open_checkpoint $p_prefix.synth.dcp -part $p_device - read_xdc $xdc_files - read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp - set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg] - opt_design > $p_prefix.${prcfg_name}_opt.rds - write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx - place_design > $p_prefix.${prcfg_name}_place.rds - route_design > $p_prefix.${prcfg_name}_route.rds - - } else { - - open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device - lock_design -level routing - read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp - read_xdc $xdc_files - opt_design > $p_prefix.${prcfg_name}_opt.rds - place_design > $p_prefix.${prcfg_name}_place.rds - route_design > $p_prefix.${prcfg_name}_route.rds - } - - write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp - report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt - report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt - - if [expr [get_property SLACK [get_timing_paths]] < 0] { - set p_prcfg_status 1 - puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!" - } - - write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp - update_design -cell i_prcfg -black_box - write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp - open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device - write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit - write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf - file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf - - if {$prcfg_name ne "default"} { - lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp" - } - - if {$prcfg_name eq "default"} { - file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf - } -} - -## Verify an implemented partial reconfiguration design, checks if all the -# partial design are compatible with the base design. -# -# \param[project_name] - project name -# -proc adi_project_verify {project_name} { - - # checkpoint for the default design - global p_prcfg_init - # list of checkpoints with all the PRs integrated into the default design - global p_prcfg_list - global p_prcfg_status - - set p_prefix "$project_name.data/$project_name" - - pr_verify -full_check -initial $p_prcfg_init \ - -additional $p_prcfg_list \ - -file $p_prefix.prcfg_verify.log - - if {$p_prcfg_status == 1} { - return -code error [format "ERROR: Timing Constraints NOT met!"] - } -} - diff --git a/CI/scripts/build_bsp.sh b/CI/scripts/build_bsp.sh index 3e25a4a1..ed48b1a1 100644 --- a/CI/scripts/build_bsp.sh +++ b/CI/scripts/build_bsp.sh @@ -84,7 +84,6 @@ cp ports.json ../hdl/vendor/AnalogDevices/+AnalogDevices/ # Updates cp scripts/matlab_processors.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl -cp scripts/adi_project_xilinx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_project_xilinx.tcl cp scripts/system_project_rxtx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl cp scripts/adi_build.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl cp scripts/adi_build_win.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build_win.tcl diff --git a/CI/scripts/dockermake b/CI/scripts/dockermake index 06c93222..a3fbc3e6 100644 --- a/CI/scripts/dockermake +++ b/CI/scripts/dockermake @@ -1,3 +1,3 @@ #!/bin/bash docker build . -t matlabci -f CI/scripts/Docker -docker run --rm -e "INCLUDE_EXAMPLES=$INCLUDE_EXAMPLES" -e "BOARD=$BOARD" -e "LM_LICENSE_FILE=$LM_LICENSE_FILE" -e "XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE" -e "MLRELEASE=$MLRELEASE" -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work" -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB -v /root/.matlab:/root/.matlabro:ro -v /root/.Xilinx:/root/.Xilinxro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'" +docker run --rm -e "INCLUDE_EXAMPLES=$INCLUDE_EXAMPLES" -e "BOARD=$BOARD" -e "LM_LICENSE_FILE=$LM_LICENSE_FILE" -e "XILINXD_LICENSE_FILE=$XILINXD_LICENSE_FILE" -e "MLRELEASE=$MLRELEASE" -e "VIVADORELEASE=$VIVADORELEASE" -e "HDLBRANCH=$HDLBRANCH" -v "$(pwd):/work" -v /mlhsp:/mlhspro:ro -v /usr/local/MATLAB:/usr/local/MATLAB -v /root/.matlab:/root/.matlabro:ro -v /root/.Xilinx:/root/.Xilinxro:ro -v /opt/Xilinx:/opt/Xilinx --mac-address="$ADDR" matlabci /bin/bash -c "cd /work && chmod +x CI/scripts/setupDocker.sh && ./CI/scripts/setupDocker.sh && make -C CI/scripts '$@'" diff --git a/CI/scripts/synth_designs.sh b/CI/scripts/synth_designs.sh index e525f762..73ca366f 100644 --- a/CI/scripts/synth_designs.sh +++ b/CI/scripts/synth_designs.sh @@ -2,7 +2,6 @@ BOARD=$1 MLFLAGS="-nodisplay -nodesktop -nosplash" - if [ -z "$MLRELEASE" ] then MLRELEASE=R2023b @@ -10,15 +9,20 @@ fi MLPATH=/usr/local/MATLAB -cd ../.. +if [ -z "$VIVADORELEASE" ] +then + VIVADORELEASE=2023.1 +fi + +cd ../.. cp hdl/vendor/AnalogDevices/hdlcoder_board_customization.m test/hdlcoder_board_customization_local.m sed -i "s/hdlcoder_board_customization/hdlcoder_board_customization_local/g" test/hdlcoder_board_customization_local.m -source /opt/Xilinx/Vivado/2022.2/settings64.sh +source /opt/Xilinx/Vivado/$VIVADORELEASE/settings64.sh Xvfb :77 & export DISPLAY=:77 export SWT_GTK3=0 -source /opt/Xilinx/Vivado/2022.2/settings64.sh -$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "cd('test');runSynthTests('$BOARD');" +source /opt/Xilinx/Vivado/$VIVADORELEASE/settings64.sh +$MLPATH/$MLRELEASE/bin/matlab $MLFLAGS -r "addpath(genpath(pwd));cd('test');runSynthTests('$BOARD');" pidof Xvfb if [ $? -eq 0 ]; then kill -9 `pidof Xvfb` diff --git a/CI/scripts/system_project_rxtx.tcl b/CI/scripts/system_project_rxtx.tcl index c13eb85f..fb0502a0 100644 --- a/CI/scripts/system_project_rxtx.tcl +++ b/CI/scripts/system_project_rxtx.tcl @@ -9,9 +9,12 @@ cd projects/$project/$carrier source ../../scripts/adi_make.tcl adi_make::lib all +set ::env(ADI_SKIP_SYNTHESIS) 1 set ::env(SKIP_SYNTHESIS) 1 +set ::env(ADI_MATLAB) 1 set ::env(MATLAB) 1 set ::env(ADI_USE_OOC_SYNTHESYS) 1 +set ::env(ADI_IGNORE_VERSION_CHECK) 1 source ./system_project.tcl @@ -29,4 +32,4 @@ save_bd_design validate_bd_design # Back to root -cd $start_dir \ No newline at end of file +cd $start_dir diff --git a/Jenkinsfile b/Jenkinsfile index 226182db..be2eadca 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -4,6 +4,7 @@ flags = gitParseFlags() dockerConfig = getDockerConfig(['MATLAB','Vivado'], matlabHSPro=false) dockerConfig.add("-e MLRELEASE=R2023b") +dockerConfig.add("-e VIVADORELEASE=2023.1") dockerHost = 'docker' //////////////////////////// @@ -127,7 +128,7 @@ node { unstash "builtSources" uploadArtifactory('HighSpeedConverterToolbox','*.mltbx') } - if (env.BRANCH_NAME == 'master') { + if (env.BRANCH_NAME == 'main') { cstage('Deploy Production', "", flags) { unstash "builtSources" uploadFTP('HighSpeedConverterToolbox','*.mltbx') diff --git a/JenkinsfileCron b/JenkinsfileCron index d5ffcb67..7ef9ac7a 100644 --- a/JenkinsfileCron +++ b/JenkinsfileCron @@ -2,6 +2,7 @@ dockerConfig = getDockerConfig(['MATLAB','Vivado'], matlabHSPro=false) dockerConfig.add("-e MLRELEASE=R2023b") +dockerConfig.add("-e VIVADORELEASE=2022.2") dockerHost = 'docker' //////////////////////////// diff --git a/Jenkinsfile_dev b/Jenkinsfile_dev new file mode 100644 index 00000000..010360b6 --- /dev/null +++ b/Jenkinsfile_dev @@ -0,0 +1,110 @@ +@Library('tfc-lib') _ + +dockerConfig = getDockerConfig(['MATLAB','Vivado'], matlabHSPro=false) +dockerConfig.add("-e MLRELEASE=R2022b") +dockerConfig.add("-e VIVADORELEASE=2022.2") +dockerHost = 'docker' + +//////////////////////////// + +hdlBranches = ['main'] + +stage("Build Toolbox") { + dockerParallelBuild(hdlBranches, dockerHost, dockerConfig) { + branchName -> + try { + withEnv(['HDLBRANCH='+branchName]) { + checkout scm + sh 'git submodule update --init' + sh 'pip3 install -r ./CI/gen_doc/requirements_doc.txt' + sh 'make -C ./CI/gen_doc doc_ml' + sh 'make -C ./CI/scripts build' + sh 'make -C ./CI/scripts gen_tlbx' + } + } catch(Exception ex) { + if (branchName == 'main') { + error('Production Toolbox Build Failed') + } + else { + unstable('Development Build Failed') + } + } + if (branchName == 'main') { + archiveArtifacts artifacts: '*.mltbx' + stash includes: '**', name: 'builtSources', useDefaultExcludes: false + } + } +} + +///////////////////////////////////////////////////// + +boardNames = ['daq2','ad9081'] +dockerConfig.add("-e HDLBRANCH=main") + +stage("HDL Tests") { + dockerParallelBuild(boardNames, dockerHost, dockerConfig) { + branchName -> + withEnv(['BOARD='+branchName]) { + stage("Source") { + unstash "builtSources" + sh 'make -C ./CI/scripts test' + junit testResults: 'test/*.xml', allowEmptyResults: true + archiveArtifacts artifacts: 'test/logs/*', followSymlinks: false, allowEmptyArchive: true + } + stage("Installer") { + unstash "builtSources" + sh 'make -C ./CI/scripts test_installer' + junit testResults: 'test/*.xml', allowEmptyResults: true + archiveArtifacts artifacts: 'test/logs/*', followSymlinks: false, allowEmptyArchive: true + } + } + } +} + +///////////////////////////////////////////////////// + +boardNames = ['NonHW'] + +stage("NonHW Tests") { + dockerParallelBuild(boardNames, dockerHost, dockerConfig) { + branchName -> + withEnv(['BOARD='+branchName]) { + stage("NonHW") { + unstash "builtSources" + sh 'make -C ./CI/scripts run_NonHWTests' + } + } + } +} + + +///////////////////////////////////////////////////// + +classNames = ['DAQ2'] + +stage("Hardware Streaming Tests") { + dockerParallelBuild(classNames, dockerHost, dockerConfig) { + branchName -> + withEnv(['HW='+branchName]) { + unstash "builtSources" + sh 'echo ${HW}' + // sh 'make -C ./CI/scripts test_streaming' + } + } +} + +////////////////////////////////////////////////////// + +node { + stage('Deploy Development') { + unstash "builtSources" + uploadArtifactory('HighSpeedConverterToolbox','*.mltbx') + } + if (env.BRANCH_NAME == 'main') { + stage('Deploy Production') { + unstash "builtSources" + uploadFTP('HighSpeedConverterToolbox','*.mltbx') + } + } +} + diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m index 5a418bde..9477bff8 100644 --- a/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m @@ -37,8 +37,7 @@ hRD.BoardName = sprintf('AnalogDevices %s %s', pname, upper(board)); % Tool information -%hRD.SupportedToolVersion = {adi.Version.Vivado}; % FIXME -hRD.SupportedToolVersion = {'2022.2'}; +hRD.SupportedToolVersion = {adi.Version.Vivado}; % Get the root directory rootDir = fileparts(strtok(mfilename('fullpath'), '+')); diff --git a/test/adi_build.tcl b/test/adi_build.tcl index 9007b7e1..c928c735 100644 --- a/test/adi_build.tcl +++ b/test/adi_build.tcl @@ -15,6 +15,8 @@ set prj_carrier $project$carrier update_compile_order -fileset sources_1 reset_run impl_1 reset_run synth_1 +set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd] +export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet launch_runs synth_1 wait_on_run synth_1 launch_runs impl_1 -to_step write_bitstream @@ -23,6 +25,7 @@ wait_on_run impl_1 # Define local variables set cdir [pwd] set sdk_loc vivado_prj.sdk +set project_system_dir vivado_prj.srcs/sources_1/bd/system # Export the hdf file delete -force $sdk_loc @@ -34,26 +37,18 @@ close_project # Create the BOOT.bin file mkdir $cdir/boot -if {$fpga_board eq "ZCU102"} { - set vversion [version -short] - exec xsct $cdir/projects/scripts/fsbl_build_zynqmp.tcl $vversion - if {[file exist boot/BOOT.BIN] eq 0} { - puts "ERROR: BOOT.BIN not built" - return -code error 11 - } else { - puts "BOOT.BIN built correctly!" - } +set xsct_script "exec xsct $cdir/projects/scripts/adi_make_boot_bin.tcl" +set arm_tr_frm_elf $cdir/projects/common/boot/bl31.elf +if {$fpga_board eq "ZCU102"} { + set uboot_elf $cdir/projects/common/boot/u-boot-zcu.elf } else { - exec xsct $cdir/projects/scripts/fsbl_build_zynq.tcl - if {[file exist boot/BOOT.BIN] eq 0} { - puts "ERROR: BOOT.BIN not built" - return -code error 11 - } else { - puts "BOOT.BIN built correctly!" - } + set uboot_elf $cdir/projects/common/boot/u-boot.elf } +set build_args "$sdk_loc/system_top.xsa $uboot_elf $cdir/boot $arm_tr_frm_elf" +puts "Please wait, this may take a few minutes." +eval $xsct_script $build_args puts "------------------------------------" puts "Embedded system build completed." puts "You may close this shell." From 0b920cd3c3b10e03ee59ef347c84790776fd4d7c Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Wed, 6 Dec 2023 10:38:39 +0200 Subject: [PATCH 2/5] Set vivado 2023.1, Matlab R2022b, HDL main branch Signed-off-by: Travis F. Collins --- +adi/Contents.m | 2 +- +adi/Version.m | 2 +- CI/gen_doc/Makefile | 6 +- CI/gen_doc/docs/_pages/install.md | 4 +- CI/gen_doc/docs/_pages/targeting.md | 6 +- CI/scripts/Makefile | 2 +- CI/scripts/build_bsp.sh | 73 ++++++++++++++---- Jenkinsfile | 3 +- JenkinsfileCron | 2 +- Jenkinsfile_dev | 110 ---------------------------- info.xml | 2 +- 11 files changed, 75 insertions(+), 137 deletions(-) delete mode 100644 Jenkinsfile_dev diff --git a/+adi/Contents.m b/+adi/Contents.m index 7e4b46cd..052026c2 100644 --- a/+adi/Contents.m +++ b/+adi/Contents.m @@ -1,5 +1,5 @@ % Analog Devices, Inc. High Speed Converter Toolbox -% Version 21.1.1 (R2021a) +% Version 21.1.1 (R2022b) % % ==== Table of Contents (TOC) ==== % diff --git a/+adi/Version.m b/+adi/Version.m index e84668c2..8f172246 100644 --- a/+adi/Version.m +++ b/+adi/Version.m @@ -3,7 +3,7 @@ % BSP Version information properties(Constant) HDL = 'hdl_2022_r2'; - Vivado = '2022.2'; + Vivado = '2023.1'; MATLAB = 'R2023b'; Release = '23.2.1'; AppName = 'Analog Devices, Inc. High-Speed Converter Toolbox'; diff --git a/CI/gen_doc/Makefile b/CI/gen_doc/Makefile index dd6b1af3..bc21b12a 100644 --- a/CI/gen_doc/Makefile +++ b/CI/gen_doc/Makefile @@ -8,15 +8,15 @@ SHELL := /bin/bash MLFLAGS := -nodisplay -nodesktop -nosplash ifeq ($(MLRELEASE),) -MLRELEASE := R2021a +MLRELEASE := R2022b endif ifeq ($(VIVADORELEASE),) -VIVADORELEASE := 2022.2 +VIVADORELEASE := 2023.1 endif ifeq ($(HDLBRANCH),) -HDLBRANCH := hdl_2018_r2 +HDLBRANCH := main endif ifeq ($(OS),Windows_NT) diff --git a/CI/gen_doc/docs/_pages/install.md b/CI/gen_doc/docs/_pages/install.md index 18280a26..c2dcafe7 100644 --- a/CI/gen_doc/docs/_pages/install.md +++ b/CI/gen_doc/docs/_pages/install.md @@ -35,8 +35,8 @@ The base dependencies for the toolbox requires libiio and the libiio MATLAB bind To leverage HDL-Coder and the reference designs with the toolbox requires the following components: -- Xilinx Vivado 2021.1 -- Xilinx SDK 2021.1 +- Xilinx Vivado 2023.1 +- Xilinx SDK 2023.1 - Simulink - [HDL-Coder™](https://www.mathworks.com/products/hdl-coder.html) - [HDL Coder™ Support Package for Xilinx Zynq Platform](https://www.mathworks.com/matlabcentral/fileexchange/40447-hdl-coder-support-package-for-xilinx-zynq-platform) diff --git a/CI/gen_doc/docs/_pages/targeting.md b/CI/gen_doc/docs/_pages/targeting.md index d6016a92..6d69f867 100644 --- a/CI/gen_doc/docs/_pages/targeting.md +++ b/CI/gen_doc/docs/_pages/targeting.md @@ -11,18 +11,18 @@ High-Speed Converter Toolbox supports the IP Core generation flow from MathWorks ## Getting Started -To perform targeting will require FPGA vendor tools for the FPGA system. For Xilinx this will be Vivado and the toolbox will require specific versions for each release. For the current release this is Vivado 2022.2. Using other versions are not supported. To build the necessary BOOT.BIN files will require the Xilinx Vitis as well. +To perform targeting will require FPGA vendor tools for the FPGA system. For Xilinx this will be Vivado and the toolbox will require specific versions for each release. For the current release this is Vivado 2023.1. Using other versions are not supported. To build the necessary BOOT.BIN files will require the Xilinx Vitis as well. Once you have the installed the necessary 3rd party tools MATLAB needs to be told where they are installed by use of the [hdlsetuptoolpath](https://www.mathworks.com/help/hdlcoder/ref/hdlsetuptoolpath.html) command. For Windows the following MATLAB command can be used: ```matlab -hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2022.2\bin\vivado.bat'); +hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2023.1\bin\vivado.bat'); ``` or Linux: ```matlab -hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', '/opt/Xilinx/Vivado/2022.2/bin/vivado'); +hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', '/opt/Xilinx/Vivado/2023.1/bin/vivado'); ``` Please change the tool path if it is different on your system. diff --git a/CI/scripts/Makefile b/CI/scripts/Makefile index 75bcc4e4..93228b5d 100644 --- a/CI/scripts/Makefile +++ b/CI/scripts/Makefile @@ -12,7 +12,7 @@ MLRELEASE := R2023b endif ifeq ($(VIVADORELEASE),) -VIVADORELEASE := 2022.2 +VIVADORELEASE := 2023.1 endif ifeq ($(HDLBRANCH),) diff --git a/CI/scripts/build_bsp.sh b/CI/scripts/build_bsp.sh index ed48b1a1..2843a5e4 100644 --- a/CI/scripts/build_bsp.sh +++ b/CI/scripts/build_bsp.sh @@ -2,7 +2,7 @@ set -x if [ -z "${HDLBRANCH}" ]; then -HDLBRANCH='hdl_2022_r2' +HDLBRANCH='main' fi # Script is designed to run from specific location @@ -29,20 +29,67 @@ if [ ! -d "hdl" ]; then exit 1 fi -# Get required vivado version needed for HDL -if [ -f "hdl/library/scripts/adi_ip.tcl" ]; then - TARGET="hdl/library/scripts/adi_ip.tcl" -else - TARGET="hdl/library/scripts/adi_ip_xilinx.tcl" +if [ -z "${VIVADO}" ]; then + echo "VIVADO not set, will parse HDL" + + # Get required vivado version needed for HDL + TARGET="hdl/scripts/adi_env.tcl" + # Use grep to find the line containing "set required_vivado_version" + matched_line=$(grep 'set required_vivado_version' "$TARGET") + + # Use awk to extract the version number + VIVADO=$(echo "$matched_line" | awk -F'"' '{print $2}') + + # Print the extracted version number + echo "Parsed Vivado Version: $VIVADO" fi -VER=$(awk '/set required_vivado_version/ {print $3}' $TARGET | sed 's/"//g') -echo "Required Vivado version ${VER}" -VIVADOFULL=${VER} -if [ ${#VER} = 8 ] -then -VER=${VER:0:6} + +# If not of the form 20xx.x, exit +if [[ ! $VIVADO =~ ^20[0-9]{2}\.[0-9]$ ]]; then + echo "Vivado version not of the form 20xx.x" + exit 1 fi -VIVADO=${VER} + +# Update vivado version in MATLAB files +echo "Updating toolbox files to use desired Vivado version" +cd .. +# Update Version.m +sed -i "s/Vivado = .*/Vivado = \'${VIVADO}\';/" +adi/Version.m +# Update plugin_rd +sed -i "s/hRD\.SupportedToolVersion = .*/hRD\.SupportedToolVersion = {\'${VIVADO}\'};/" hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m + +# Demos +cd trx_examples +# Update all occurances of hWC.ReferenceDesignToolVersion = '20XX.X'; to use new version +FILES=$(grep -lrn . -e 'hWC.ReferenceDesignToolVersion =') +for f in $FILES; do + echo "Updating: $f" + sed -i "s/hWC\.ReferenceDesignToolVersion = .*/hWC\.ReferenceDesignToolVersion = \'${VIVADO}\';/" "$f" +done +# Update all occurances of hRD.SupportedToolVersion = {'20XX.X'}; to use new version +FILES=$(grep -lr . -e 'hRD.SupportedToolVersion =') +for f in $FILES; do + echo "Updating: $f" + sed -i "s/hRD\.SupportedToolVersion = .*/hRD\.SupportedToolVersion = {\'${VIVADO}\'};/" "$f" +done +# Update all occurances of Vivado sourcing +FILES=$(grep -lrn . -e 'source /opt/Xilinx/Vivado/20') +for f in $FILES; do + echo "Updating: $f" + sed -i "s/source \/opt\/Xilinx\/Vivado\/20.*/source \/opt\/Xilinx\/Vivado\/${VIVADO}\/settings64.sh/" "$f" +done +cd .. + +# Tests +cd test +# Update line 35 of DemoTests.m to use new version +sed -i "35s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m +sed -i "47s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m +sed -i "59s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m + +cd .. + +cd CI # Setup source /opt/Xilinx/Vivado/$VIVADO/settings64.sh diff --git a/Jenkinsfile b/Jenkinsfile index be2eadca..f73b4163 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -19,7 +19,8 @@ stage("Build Toolbox") { checkout scm sh 'git submodule update --init' sh 'pip3 install -r ./CI/gen_doc/requirements_doc.txt' - sh 'make -C ./CI/gen_doc doc_ml' + sh 'rm -rf doc || true' + sh 'make -C ./CI/gen_doc doc_ml' sh 'make -C ./CI/scripts build' sh 'make -C ./CI/scripts gen_tlbx' } diff --git a/JenkinsfileCron b/JenkinsfileCron index 7ef9ac7a..48c17d9f 100644 --- a/JenkinsfileCron +++ b/JenkinsfileCron @@ -2,7 +2,7 @@ dockerConfig = getDockerConfig(['MATLAB','Vivado'], matlabHSPro=false) dockerConfig.add("-e MLRELEASE=R2023b") -dockerConfig.add("-e VIVADORELEASE=2022.2") +dockerConfig.add("-e VIVADORELEASE=2023.1") dockerHost = 'docker' //////////////////////////// diff --git a/Jenkinsfile_dev b/Jenkinsfile_dev deleted file mode 100644 index 010360b6..00000000 --- a/Jenkinsfile_dev +++ /dev/null @@ -1,110 +0,0 @@ -@Library('tfc-lib') _ - -dockerConfig = getDockerConfig(['MATLAB','Vivado'], matlabHSPro=false) -dockerConfig.add("-e MLRELEASE=R2022b") -dockerConfig.add("-e VIVADORELEASE=2022.2") -dockerHost = 'docker' - -//////////////////////////// - -hdlBranches = ['main'] - -stage("Build Toolbox") { - dockerParallelBuild(hdlBranches, dockerHost, dockerConfig) { - branchName -> - try { - withEnv(['HDLBRANCH='+branchName]) { - checkout scm - sh 'git submodule update --init' - sh 'pip3 install -r ./CI/gen_doc/requirements_doc.txt' - sh 'make -C ./CI/gen_doc doc_ml' - sh 'make -C ./CI/scripts build' - sh 'make -C ./CI/scripts gen_tlbx' - } - } catch(Exception ex) { - if (branchName == 'main') { - error('Production Toolbox Build Failed') - } - else { - unstable('Development Build Failed') - } - } - if (branchName == 'main') { - archiveArtifacts artifacts: '*.mltbx' - stash includes: '**', name: 'builtSources', useDefaultExcludes: false - } - } -} - -///////////////////////////////////////////////////// - -boardNames = ['daq2','ad9081'] -dockerConfig.add("-e HDLBRANCH=main") - -stage("HDL Tests") { - dockerParallelBuild(boardNames, dockerHost, dockerConfig) { - branchName -> - withEnv(['BOARD='+branchName]) { - stage("Source") { - unstash "builtSources" - sh 'make -C ./CI/scripts test' - junit testResults: 'test/*.xml', allowEmptyResults: true - archiveArtifacts artifacts: 'test/logs/*', followSymlinks: false, allowEmptyArchive: true - } - stage("Installer") { - unstash "builtSources" - sh 'make -C ./CI/scripts test_installer' - junit testResults: 'test/*.xml', allowEmptyResults: true - archiveArtifacts artifacts: 'test/logs/*', followSymlinks: false, allowEmptyArchive: true - } - } - } -} - -///////////////////////////////////////////////////// - -boardNames = ['NonHW'] - -stage("NonHW Tests") { - dockerParallelBuild(boardNames, dockerHost, dockerConfig) { - branchName -> - withEnv(['BOARD='+branchName]) { - stage("NonHW") { - unstash "builtSources" - sh 'make -C ./CI/scripts run_NonHWTests' - } - } - } -} - - -///////////////////////////////////////////////////// - -classNames = ['DAQ2'] - -stage("Hardware Streaming Tests") { - dockerParallelBuild(classNames, dockerHost, dockerConfig) { - branchName -> - withEnv(['HW='+branchName]) { - unstash "builtSources" - sh 'echo ${HW}' - // sh 'make -C ./CI/scripts test_streaming' - } - } -} - -////////////////////////////////////////////////////// - -node { - stage('Deploy Development') { - unstash "builtSources" - uploadArtifactory('HighSpeedConverterToolbox','*.mltbx') - } - if (env.BRANCH_NAME == 'main') { - stage('Deploy Production') { - unstash "builtSources" - uploadFTP('HighSpeedConverterToolbox','*.mltbx') - } - } -} - diff --git a/info.xml b/info.xml index 7e3b3a6c..35038946 100644 --- a/info.xml +++ b/info.xml @@ -8,7 +8,7 @@ - R2021a + R2022b Analog Devices, Inc. High Speed Converter Toolbox From 4954320d8cd29c8475d91b3b49af6b7c9db82b3b Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 19 Dec 2023 10:15:22 +0200 Subject: [PATCH 3/5] requirements: Mkdocs <=1.5.3 --- CI/gen_doc/requirements_doc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CI/gen_doc/requirements_doc.txt b/CI/gen_doc/requirements_doc.txt index 060c0f8f..9042c2c8 100644 --- a/CI/gen_doc/requirements_doc.txt +++ b/CI/gen_doc/requirements_doc.txt @@ -1,5 +1,5 @@ numpy -mkdocs<1.5 +mkdocs<=1.5.3 mkdocs-material mkdocs-awesome-pages-plugin mkdocs-mermaid2-plugin From 557b5b65a9f568fe4bc7f541bbeffa99c498af5a Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 14 Oct 2024 13:56:57 +0300 Subject: [PATCH 4/5] Version: Use a constructor to set Vivado version dynamically --- +adi/Version.m | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/+adi/Version.m b/+adi/Version.m index 8f172246..34e97a89 100644 --- a/+adi/Version.m +++ b/+adi/Version.m @@ -3,7 +3,6 @@ % BSP Version information properties(Constant) HDL = 'hdl_2022_r2'; - Vivado = '2023.1'; MATLAB = 'R2023b'; Release = '23.2.1'; AppName = 'Analog Devices, Inc. High-Speed Converter Toolbox'; @@ -12,13 +11,27 @@ ExamplesDir = 'hsx_examples'; HasHDL = true; end - properties(Dependent) + + properties + Vivado + end + + properties(Dependent) VivadoShort end - - methods + +methods + % Set Vivado version dynamically + function obj = Version(vivado_version) + if nargin > 0 + obj.Vivado = vivado_version; % Set Vivado based on input + else + obj.Vivado = '2023.1'; % Default value + end + end + function value = get.VivadoShort(obj) - value = obj.Vivado(1:6); + value = obj.Vivado(1:6); end end end From f599c38c4638cf7dea9890990b9a63b83e2c77c2 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 14 Oct 2024 14:59:52 +0300 Subject: [PATCH 5/5] Rebase the build_bsp.sh --- CI/scripts/build_bsp.sh | 74 ++++++++--------------------------------- 1 file changed, 14 insertions(+), 60 deletions(-) diff --git a/CI/scripts/build_bsp.sh b/CI/scripts/build_bsp.sh index 2843a5e4..dca29ca2 100644 --- a/CI/scripts/build_bsp.sh +++ b/CI/scripts/build_bsp.sh @@ -29,67 +29,20 @@ if [ ! -d "hdl" ]; then exit 1 fi -if [ -z "${VIVADO}" ]; then - echo "VIVADO not set, will parse HDL" - - # Get required vivado version needed for HDL - TARGET="hdl/scripts/adi_env.tcl" - # Use grep to find the line containing "set required_vivado_version" - matched_line=$(grep 'set required_vivado_version' "$TARGET") - - # Use awk to extract the version number - VIVADO=$(echo "$matched_line" | awk -F'"' '{print $2}') - - # Print the extracted version number - echo "Parsed Vivado Version: $VIVADO" +# Get required vivado version needed for HDL +if [ -f "hdl/library/scripts/adi_ip.tcl" ]; then + TARGET="hdl/library/scripts/adi_ip.tcl" +else + TARGET="hdl/library/scripts/adi_ip_xilinx.tcl" fi - -# If not of the form 20xx.x, exit -if [[ ! $VIVADO =~ ^20[0-9]{2}\.[0-9]$ ]]; then - echo "Vivado version not of the form 20xx.x" - exit 1 +VER=$(awk '/set required_vivado_version/ {print $3}' $TARGET | sed 's/"//g') +echo "Required Vivado version ${VER}" +VIVADOFULL=${VER} +if [ ${#VER} = 8 ] +then +VER=${VER:0:6} fi - -# Update vivado version in MATLAB files -echo "Updating toolbox files to use desired Vivado version" -cd .. -# Update Version.m -sed -i "s/Vivado = .*/Vivado = \'${VIVADO}\';/" +adi/Version.m -# Update plugin_rd -sed -i "s/hRD\.SupportedToolVersion = .*/hRD\.SupportedToolVersion = {\'${VIVADO}\'};/" hdl/vendor/AnalogDevices/+AnalogDevices/plugin_rd.m - -# Demos -cd trx_examples -# Update all occurances of hWC.ReferenceDesignToolVersion = '20XX.X'; to use new version -FILES=$(grep -lrn . -e 'hWC.ReferenceDesignToolVersion =') -for f in $FILES; do - echo "Updating: $f" - sed -i "s/hWC\.ReferenceDesignToolVersion = .*/hWC\.ReferenceDesignToolVersion = \'${VIVADO}\';/" "$f" -done -# Update all occurances of hRD.SupportedToolVersion = {'20XX.X'}; to use new version -FILES=$(grep -lr . -e 'hRD.SupportedToolVersion =') -for f in $FILES; do - echo "Updating: $f" - sed -i "s/hRD\.SupportedToolVersion = .*/hRD\.SupportedToolVersion = {\'${VIVADO}\'};/" "$f" -done -# Update all occurances of Vivado sourcing -FILES=$(grep -lrn . -e 'source /opt/Xilinx/Vivado/20') -for f in $FILES; do - echo "Updating: $f" - sed -i "s/source \/opt\/Xilinx\/Vivado\/20.*/source \/opt\/Xilinx\/Vivado\/${VIVADO}\/settings64.sh/" "$f" -done -cd .. - -# Tests -cd test -# Update line 35 of DemoTests.m to use new version -sed -i "35s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m -sed -i "47s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m -sed -i "59s/.*/ testCase.setupVivado('${VIVADO}');/" DemoTests.m - -cd .. - -cd CI +VIVADO=${VER} # Setup source /opt/Xilinx/Vivado/$VIVADO/settings64.sh @@ -131,6 +84,7 @@ cp ports.json ../hdl/vendor/AnalogDevices/+AnalogDevices/ # Updates cp scripts/matlab_processors.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl +cp scripts/adi_project_xilinx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_project_xilinx.tcl cp scripts/system_project_rxtx.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/system_project_rxtx.tcl cp scripts/adi_build.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build.tcl cp scripts/adi_build_win.tcl ../hdl/vendor/AnalogDevices/vivado/projects/scripts/adi_build_win.tcl @@ -145,4 +99,4 @@ cp scripts/fixmake.sh ../hdl/vendor/AnalogDevices/vivado/projects/scripts/fixma mkdir ../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ cp -r scripts/boot/* ../hdl/vendor/AnalogDevices/vivado/projects/common/boot/ -echo 'puts "Skipping"' > ../hdl/vendor/AnalogDevices/vivado/library/axi_ad9361/axi_ad9361_delay.tcl +echo 'puts "Skipping"' > ../hdl/vendor/AnalogDevices/vivado/library/axi_ad9361/axi_ad9361_delay.tcl \ No newline at end of file