From e6c91707672a416651758b5e3081c425b32bb42a Mon Sep 17 00:00:00 2001 From: Yizhou Shan Date: Tue, 25 Jan 2022 10:07:10 -0800 Subject: [PATCH] Update README.md --- README.md | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/README.md b/README.md index a5a27bd..e56af5c 100644 --- a/README.md +++ b/README.md @@ -1,11 +1,17 @@ -# Clio Artifact +# Clio System -Clio is a Hardware-Software Co-Designed Disaggregated Memory System. -The paper has been accepted to ASPLOS'22. -We are still working on the final version. -You can find a pre-publication version [here](https://arxiv.org/pdf/2108.03492.pdf). +Clio is a disaggregated memory system that virtualizes, +protects, and manages disaggregated memory at hardware-based +memory nodes. More details in our ASPLOS'22 paper [here](https://arxiv.org/pdf/2108.03492.pdf). -**ASPLOS'22 Artifact Evaluators, please see [Documentation/asplos-ae.md](./Documentation/asplos-ae.md).** +This repo contains Clio's FPGA hardware design, host side software, and testing program. + +## System Architetcure + +The Clio hardware includes a new virtual memory +system, a customized network system, and a framework for computation offloading + +drawing ## Documentation @@ -17,6 +23,8 @@ To run Clio, see [Documentation/run.md](./Documentation/run.md). To debug Clio, see [Documentation/debug.md](./Documentation/debug.md). +**ASPLOS'22 Artifact Evaluators, please see [Documentation/asplos-ae.md](./Documentation/asplos-ae.md).** + ## Repo Layout High-level layout: