diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/README.md" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/README.md" new file mode 100644 index 0000000..c650c68 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/README.md" @@ -0,0 +1,16 @@ +### 2020 年春季学期 COD 实验报告 & 代码 + +原项目/历史记录请见 https://github.com/ustcpetergu/USTC-COD-Labs/ + +- Lab1: ALU & sort +- Lab2: Regfile & RAM & FIFO +- Lab3: Single cycle CPU +- Lab4: Multiple cycle CPU +- Lab5: 5-stage pipeline CPU +- Lab6: CPU & UART on ebaz4205 (testing video in report.md) + +Rebuild projects from TCL(for example): + +``` +vivado -mode batch -source lab6.tcl -tclargs --project_name lab6 +``` \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/component.xml" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/component.xml" new file mode 100644 index 0000000..053ccd2 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/component.xml" @@ -0,0 +1,276 @@ + + + ustcpetergu.com + user + alu + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + alu + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7bf5aeae + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + alu + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 7bf5aeae + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + sort_simu + + xilinx_testbench_view_fileset + + + + viewChecksum + 079ef021 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b030f5a2 + + + + + + + m + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + a + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + b + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + y + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + zf + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cf + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + of + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + WIDTH + Width + 32 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/alu.v + verilogSource + CHECKSUM_7bf5aeae + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/alu.v + verilogSource + IMPORTED_FILE + + + + xilinx_testbench_view_fileset + + src/sort_simu.v + verilogSource + IMPORTED_FILE + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + + xilinx_xpgui_view_fileset + + xgui/alu_v1_0.tcl + tclSource + CHECKSUM_b030f5a2 + XGUI_VERSION_2 + + + + alu_v1_0 + + + WIDTH + Width + 32 + + + Component_Name + alu_v1_0 + + + + + + artix7 + artix7l + aartix7 + zynq + azynq + + + /UserIP + + alu_v1_0 + package_project + 1 + + user.org:user:alu:1.0 + + 2020-05-06T13:03:33Z + + /home/petergu/MyHome/COD/ip + /home/petergu/MyHome/COD/ip + /home/petergu/MyHome/COD/ip + /home/petergu/MyHome/COD/ip + /home/petergu/MyHome/COD/ip + /home/petergu/MyHome/COD/ip + /home/petergu/MyHome/COD/ip + + + + 2019.1 + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/src/alu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/src/alu.v" new file mode 100755 index 0000000..af53a11 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/src/alu.v" @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +// ALU +// 2020 COD Lab1 +// ustcpetergu + +module alu + #(parameter WIDTH = 32) + ( + input [2:0]m, // selection + input [WIDTH-1:0]a, b, // input + output [WIDTH-1:0]y, // result + output zf, // zero flag + output cf, // carry out flag: WIDTH bit + output of // overflow flag: WIDTH-1 sign bit + ); + + reg [WIDTH-1:0]regy; + reg regcf; + reg regof; + reg regzf; + assign y = regy; + assign cf = regcf; + assign of = regof; + assign zf = regzf; + // assign zf = (regy == 0); + + always @ (a, b, m) begin + case(m) + 3'b000: begin // add + {regcf, regy} = a + b; + regof = (!a[WIDTH-1] & !b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b001: begin // sub + {regcf, regy} = a - b; + regof = (!a[WIDTH-1] & b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & !b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b010: begin // and + regy = a & b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b011: begin // or + regy = a | b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b100: begin // xor + regy = a ^ b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + default: begin // error + regy = 0; + regzf = 0; + regcf = 0; + regof = 0; + end + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/src/sort_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/src/sort_simu.v" new file mode 100755 index 0000000..6a4ca29 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/src/sort_simu.v" @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +// sort simulation +// 2020 COD Lab1 +// ustcpetergu + +module sort_simu(); + reg clk, rst; + reg [3:0] i1, i2, i3, i4; + wire [3:0] o1, o2, o3, o4; + wire done; + + sort #(.N(4)) sort_inst + ( + .i1(i1), + .i2(i2), + .i3(i3), + .i4(i4), + .clk(clk), + .rst(rst), + .o1(o1), + .o2(o2), + .o3(o3), + .o4(o4), + .done(done) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + i1 = 9; + i2 = 3; + i3 = 8; + i4 = 1; + rst = 1; + #10 + rst = 0; + + #(10 * 7) + + rst = 1; + #10 + rst = 0; + + i1 = 8; + i2 = 10; + i3 = 15; + i4 = 11; + #(10 * 7) + + rst = 1; + #10 + rst = 0; + + i1 = 4; + i2 = 3; + i3 = 2; + i4 = 1; + #(10 * 7) + + #10 + $finish; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/xgui/alu_v1_0.tcl" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/xgui/alu_v1_0.tcl" new file mode 100644 index 0000000..f00d37a --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/alu/xgui/alu_v1_0.tcl" @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { + # Procedure called to update WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { + # Procedure called to validate WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH} +} + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/edgefetcher/component.xml" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/edgefetcher/component.xml" new file mode 100644 index 0000000..628f59d --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/edgefetcher/component.xml" @@ -0,0 +1,328 @@ + + + ustcpetergu.com + user + edgefetcher + 1.0 + + + rst + + + + + + + RST + + + rst + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rst + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + edgefetcher + + xilinx_anylanguagesynthesis_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + ab728d6c + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + edgefetcher + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + ab728d6c + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + fifo_simu + + xilinx_testbench_view_fileset + + + + viewChecksum + 922ad8b7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + y + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/dist_mem_gen_0/dist_mem_gen_0.xci + xci + IMPORTED_FILE + + + src/fifo.v + verilogSource + IMPORTED_FILE + + + src/ram_16x8.v + verilogSource + IMPORTED_FILE + + + src/register_file.v + verilogSource + IMPORTED_FILE + + + src/edgefetcher.v + verilogSource + CHECKSUM_69b5556d + IMPORTED_FILE + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/dist_mem_gen_0/dist_mem_gen_0.xci + xci + IMPORTED_FILE + + + src/fifo.v + verilogSource + IMPORTED_FILE + + + src/ram_16x8.v + verilogSource + IMPORTED_FILE + + + src/register_file.v + verilogSource + IMPORTED_FILE + + + src/edgefetcher.v + verilogSource + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + + + + + + + + xilinx_testbench_view_fileset + + src/fifo_simu.v + verilogSource + IMPORTED_FILE + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + src/regfile_simu.v + verilogSource + IMPORTED_FILE + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + src/mem_simu.v + verilogSource + IMPORTED_FILE + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + + xilinx_xpgui_view_fileset + + xgui/edgefetcher_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + edgefetcher_v1_0 + + + Component_Name + edgefetcher_v1_0 + + + + + + artix7 + artix7l + aartix7 + zynq + azynq + + + /UserIP + + edgefetcher_v1_0 + package_project + 1 + + user.org:user:edgefetcher:1.0 + + 2020-05-07T12:33:25Z + + /home/petergu/MyHome/COD/ip/edgefetcher + /home/petergu/MyHome/COD/ip/edgefetcher + /home/petergu/MyHome/COD/ip/edgefetcher + /home/petergu/MyHome/COD/ip/edgefetcher + + + + 2019.1 + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/regfile/component.xml" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/regfile/component.xml" new file mode 100644 index 0000000..89987ee --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/ip/regfile/component.xml" @@ -0,0 +1,365 @@ + + + ustcpetergu.com + user + register_file + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + register_file + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 60ffed4d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + register_file + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 60ffed4d + + + + + xilinx_testbench + Test Bench + :vivado.xilinx.com:simulation.testbench + cpu_multi_cycle_simu + + xilinx_testbench_view_fileset + + + + viewChecksum + 837e8863 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b030f5a2 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ra0 + + in + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ra1 + + in + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ra2 + + in + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wa + + in + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + we + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wd + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd0 + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd1 + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd2 + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + WIDTH + Width + 32 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/test.coe + coe + IMPORTED_FILE + + + src/instr_rom.coe + coe + IMPORTED_FILE + + + src/register_file.v + verilogSource + CHECKSUM_6d8b2ad2 + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + src/test.coe + coe + IMPORTED_FILE + + + src/instr_rom.coe + coe + IMPORTED_FILE + + + src/register_file.v + verilogSource + IMPORTED_FILE + + + + xilinx_testbench_view_fileset + + src/cpu-multi-cycle-simu.v + verilogSource + IMPORTED_FILE + USED_IN_implementation + USED_IN_simulation + USED_IN_synthesis + + + + xilinx_xpgui_view_fileset + + xgui/register_file_v1_0.tcl + tclSource + CHECKSUM_b030f5a2 + XGUI_VERSION_2 + + + + register_file_v1_0 + + + WIDTH + Width + 32 + + + Component_Name + register_file_v1_0 + + + + + + zynq + + + /UserIP + + register_file_v1_0 + package_project + 1 + + user.org:user:register_file:1.0 + + 2020-05-27T11:49:13Z + + /home/petergu/MyHome/COD/ip/regfile + /home/petergu/MyHome/COD/ip/regfile + /home/petergu/MyHome/COD/ip/regfile + /home/petergu/MyHome/COD/ip/regfile + /home/petergu/MyHome/COD/ip/regfile + /home/petergu/MyHome/COD/ip/regfile + + + + 2019.1 + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/diag1.drawio" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/diag1.drawio" new file mode 100644 index 0000000..c81b57f --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/diag1.drawio" @@ -0,0 +1 @@ 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"a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/diag1.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/diag1.png" new file mode 100644 index 0000000..49fb1ce Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/diag1.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/alu_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/alu_simu.v" new file mode 100644 index 0000000..f7bda14 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/alu_simu.v" @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +// ALU simulation +// 2020 COD Lab1 +// ustcpetergu + +module alu_simu(); + reg [3:0] a, b; + reg [2:0] m; + wire [3:0] y; + wire zf, cf, of; + + alu #(.WIDTH(4)) alu_inst + ( + .m(m), .a(a), .b(b), .y(y), .zf(zf), .cf(cf), .of(of) + ); + + initial begin + m = 3'b000; // add + a = 4'b0011; + b = 4'b1100; + + #10; + a = 4'b1000; + b = 4'b1101; + + #10; + a = 4'b0101; + b = 4'b1001; + + #10; + a = 4'b1111; + b = 4'b0001; + + #10 m = 3'b001; // sub + + #10; + a = 4'b0011; + b = 4'b1110; + + #10; + a = 4'b1000; + b = 4'b1101; + + #10; + a = 4'b0101; + b = 4'b1001; + + #10; + a = 4'b0111; + b = 4'b0111; + + #10 m = 3'b010; // and + a = 4'b0011; + b = 4'b0101; + + #10 m = 3'b011; // or + #10 m = 3'b100; // xor + #10 m = 3'b101; // err + #10; + $finish; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/sort_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/sort_simu.v" new file mode 100644 index 0000000..6a4ca29 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/sort_simu.v" @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +// sort simulation +// 2020 COD Lab1 +// ustcpetergu + +module sort_simu(); + reg clk, rst; + reg [3:0] i1, i2, i3, i4; + wire [3:0] o1, o2, o3, o4; + wire done; + + sort #(.N(4)) sort_inst + ( + .i1(i1), + .i2(i2), + .i3(i3), + .i4(i4), + .clk(clk), + .rst(rst), + .o1(o1), + .o2(o2), + .o3(o3), + .o4(o4), + .done(done) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + i1 = 9; + i2 = 3; + i3 = 8; + i4 = 1; + rst = 1; + #10 + rst = 0; + + #(10 * 7) + + rst = 1; + #10 + rst = 0; + + i1 = 8; + i2 = 10; + i3 = 15; + i4 = 11; + #(10 * 7) + + rst = 1; + #10 + rst = 0; + + i1 = 4; + i2 = 3; + i3 = 2; + i4 = 1; + #(10 * 7) + + #10 + $finish; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/alu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/alu.v" new file mode 100644 index 0000000..af53a11 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/alu.v" @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +// ALU +// 2020 COD Lab1 +// ustcpetergu + +module alu + #(parameter WIDTH = 32) + ( + input [2:0]m, // selection + input [WIDTH-1:0]a, b, // input + output [WIDTH-1:0]y, // result + output zf, // zero flag + output cf, // carry out flag: WIDTH bit + output of // overflow flag: WIDTH-1 sign bit + ); + + reg [WIDTH-1:0]regy; + reg regcf; + reg regof; + reg regzf; + assign y = regy; + assign cf = regcf; + assign of = regof; + assign zf = regzf; + // assign zf = (regy == 0); + + always @ (a, b, m) begin + case(m) + 3'b000: begin // add + {regcf, regy} = a + b; + regof = (!a[WIDTH-1] & !b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b001: begin // sub + {regcf, regy} = a - b; + regof = (!a[WIDTH-1] & b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & !b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b010: begin // and + regy = a & b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b011: begin // or + regy = a | b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b100: begin // xor + regy = a ^ b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + default: begin // error + regy = 0; + regzf = 0; + regcf = 0; + regof = 0; + end + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/sort.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/sort.v" new file mode 100644 index 0000000..0c6d02a --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/sort.v" @@ -0,0 +1,160 @@ +`timescale 1ns / 1ps +// sort +// 2020 COD Lab1 +// ustcpetergu + +module sort + #(parameter N = 4) + ( + input [N-1:0]i1, i2, i3, i4, + input clk, rst, + output reg [N-1:0]o1, o2, o3, o4, + output reg done + ); + + reg [N-1:0]a, b; + wire [2:0]m = 3'b001; // minus + wire of; + wire zf; + wire [N-1:0]y; + wire sf; + assign sf = y[N-1]; + assign gt = (~of & ~sf & ~zf) | (of & sf & ~zf); + alu #(.WIDTH(N)) alu_inst + ( + .m(m), + .a(a), + .b(b), + .of(of), + .zf(zf), + .y(y) + ); + + reg [3:0]curr_state; + // reg [3:0]next_state; + + always @ (posedge clk) begin + if (rst) begin + done <= 0; + curr_state <= 4'b0000; + end + // curr_state <= next_state; + else begin case (curr_state) + 4'b0000: begin + o1 <= i1; + o2 <= i2; + o3 <= i3; + o4 <= i4; + a <= i1; + b <= i2; + curr_state <= 4'b0001; + end + 4'b0001: begin + if (gt) begin + o1 <= o2; + a <= o2; + o2 <= o1; + end + else a <= o1; + b <= o3; + curr_state <= 4'b0010; + end + 4'b0010: begin + if (gt) begin + o1 <= o3; + a <= o3; + o3 <= o1; + end + else a <= o1; + b <= o4; + curr_state <= 4'b0011; + end + 4'b0011: begin + if (gt) begin + o1 <= o4; + o4 <= o1; + // now o1 contains maximum + end + a <= o2; + b <= o3; + curr_state <= 4'b0100; + end + 4'b0100: begin + if (gt) begin + o2 <= o3; + a <= o3; + o3 <= o2; + end + else a <= o2; + b <= o4; + curr_state <= 4'b0101; + end + 4'b0101: begin + if (gt) begin + o2 <= o4; + o4 <= o2; + // now o2 contains second-max + end + a <= o3; + b <= o4; + curr_state <= 4'b0110; + end + 4'b0110: begin + if (gt) begin + o3 <= o4; + o4 <= o3; + // in order now + end + done <= 1; + curr_state <= 4'b0111; + end + 4'b0111: begin + curr_state <= 4'b0111; + end + endcase + end + end + + // reg [N-1:0]t; + // always @ (*) begin + // case (curr_state) + // 4'b0000: begin + // done = 0; + // o1 = i1; + // o2 = i2; + // o3 = i3; + // o4 = i4; + // a = o1; + // b = o2; + // next_state = 4'b0001; + // end + // 4'b0001: begin + // if (cf == 1) begin + // t = o1; + // o1 = o2; + // o2 = t; + // end + // a = o1; + // b = o3; + // next_state = 4'b0010; + // end + // 4'b0010: begin + // if (cf == 1) begin + // t = o1; + // o1 = o3; + // o3 = t; + // end + // a = o1; + // b = o4; + // next_state = 4'b0011; + // end + // 4'b0011: begin + // // if (cf == 1) begin + // // end else b = i3; + // // next_state = 4'b0100; + // end + // 4'b1111: next_state = 4'b1111; + // default: next_state = 4'b1111; + // endcase + // end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1.tcl" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1.tcl" new file mode 100644 index 0000000..7383402 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/lab1.tcl" @@ -0,0 +1,498 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1 (64-bit) +# +# lab1.tcl: Tcl script for re-creating project 'lab1-alu-sort' +# +# Generated by Vivado on Fri Apr 24 20:03:27 CST 2020 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (lab1.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "/home/petergu/MyHome/COD/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/alu.v" +# "/home/petergu/MyHome/COD/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/sort.v" +# "/home/petergu/MyHome/COD/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/sort_simu.v" +# "/home/petergu/MyHome/COD/lab1/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/alu_simu.v" +# +# 3. The following remote source files that were added to the original project:- +# +# +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "lab1-alu-sort" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "lab1.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/lab1-alu-sort"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "www.digilentinc.com:pynq-z1:part0:1.0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "pynq-z1" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "9" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/alu.v" ]\ + [file normalize "${origin_dir}/lab1-alu-sort/lab1-alu-sort.srcs/sources_1/new/sort.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "sort" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/sort_simu.v" ]\ + [file normalize "${origin_dir}/lab1-alu-sort/lab1-alu-sort.srcs/sim_1/new/alu_simu.v" ]\ +] +set imported_files [import_files -fileset sim_1 $files] + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "sort_simu" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/pic1.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/pic1.png" new file mode 100644 index 0000000..6e4dfbc Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/pic1.png" differ diff --git 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"a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/pic4.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/pic4.png" new file mode 100644 index 0000000..aa84c7e Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/pic4.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/report.md" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/report.md" new file mode 100644 index 0000000..908c044 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/report.md" @@ -0,0 +1,230 @@ +## Lab1 ALU&Sort Report + +古宜民 PB17000002 + +2020.4.26 + +### ALU设计与仿真 + +算数逻辑单元需要对于不同的操作方式m对输入的a, b进行不同的运算，并判断计算结果设置状态变量（cf, zf, of）。使用纯组合逻辑即可。对于合法的运算，需要判断结果是否为0，设置zf；对于加减，判断是否溢出（即最高位符号位是否变化异常）以及是否进位（即两个N位数加减得到N+1位数，第N+1位是否变为1）。 + +代码： + +```verilog +module alu + #(parameter WIDTH = 32) + ( + input [2:0]m, // selection + input [WIDTH-1:0]a, b, // input + output [WIDTH-1:0]y, // result + output zf, // zero flag + output cf, // carry out flag: WIDTH bit + output of // overflow flag: WIDTH-1 sign bit + ); + + reg [WIDTH-1:0]regy; + reg regcf; + reg regof; + reg regzf; + assign y = regy; + assign cf = regcf; + assign of = regof; + assign zf = regzf; + + always @ (a, b, m) begin + case(m) + 3'b000: begin // add + {regcf, regy} = a + b; + regof = (!a[WIDTH-1] & !b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b001: begin // sub + {regcf, regy} = a - b; + regof = (!a[WIDTH-1] & b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & !b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b010: begin // and + regy = a & b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b011: begin // or + regy = a | b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b100: begin // xor + regy = a ^ b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + default: begin // error + regy = 0; + regzf = 0; + regcf = 0; + regof = 0; + end + endcase + end +endmodule +``` + +仿真结果： + +radix:unsigned decimal + +![](pic1.png) + +radix:signed decimal + +![](pic2.png) + +从左到右的操作为：3+12=15, 8+13-16=5, 5+9=14, 15+1-16=0, 15-1=14, 3-14+16=5, 8-13+16=11, 5-9+16=12, 7-7=0; + +可以看到相加进位、相减退位时cf=1。radix调到signed demical，可以看到负数相加得到正数、正数减负数得到负数时of=1。 + +0011&0101=0001, 0011|0101=0111, 0011&0101=0110, 有错误时全部输出0. + +### sort设计与仿真 + +使用类似选择排序的算法，每次将两个数送到ALU中判断大小，然后在下一个周期中依据结果判读是否交换两个数。有符号数相减判断大小的条件为：若A>B, 则gt = (~of & ~sf & ~zf) | (of & sf & ~zf)为1. + +FSM如图，7个周期完成4个数的排序： + +![](diag1.png) + +仿真结果： + +![](pic3.png) + +可见reset结束后7个周期done信号发出，有符号数排序完成。 + +代码： + +```verilog +module sort + #(parameter N = 4) + ( + input [N-1:0]i1, i2, i3, i4, + input clk, rst, + output reg [N-1:0]o1, o2, o3, o4, + output reg done + ); + + reg [N-1:0]a, b; + wire [2:0]m = 3'b001; // minus + wire of; + wire zf; + wire [N-1:0]y; + wire sf; + assign sf = y[N-1]; + assign gt = (~of & ~sf & ~zf) | (of & sf & ~zf); + alu #(.WIDTH(N)) alu_inst + ( + .m(m), + .a(a), + .b(b), + .of(of), + .zf(zf), + .y(y) + ); + + reg [3:0]curr_state; + // reg [3:0]next_state; + + always @ (posedge clk) begin + if (rst) begin + done <= 0; + curr_state <= 4'b0000; + end + // curr_state <= next_state; + else begin case (curr_state) + 4'b0000: begin + o1 <= i1; + o2 <= i2; + o3 <= i3; + o4 <= i4; + a <= i1; + b <= i2; + curr_state <= 4'b0001; + end + 4'b0001: begin + if (gt) begin + o1 <= o2; + a <= o2; + o2 <= o1; + end + else a <= o1; + b <= o3; + curr_state <= 4'b0010; + end + 4'b0010: begin + if (gt) begin + o1 <= o3; + a <= o3; + o3 <= o1; + end + else a <= o1; + b <= o4; + curr_state <= 4'b0011; + end + 4'b0011: begin + if (gt) begin + o1 <= o4; + o4 <= o1; + // now o1 contains maximum + end + a <= o2; + b <= o3; + curr_state <= 4'b0100; + end + 4'b0100: begin + if (gt) begin + o2 <= o3; + a <= o3; + o3 <= o2; + end + else a <= o2; + b <= o4; + curr_state <= 4'b0101; + end + 4'b0101: begin + if (gt) begin + o2 <= o4; + o4 <= o2; + // now o2 contains second-max + end + a <= o3; + b <= o4; + curr_state <= 4'b0110; + end + 4'b0110: begin + if (gt) begin + o3 <= o4; + o4 <= o3; + // in order now + end + done <= 1; + curr_state <= 4'b0111; + end + 4'b0111: begin + curr_state <= 4'b0111; + end + endcase + end + end +endmodule +``` + +查看生产的RTL电路图，可以看到多个MUX构成输入线、ALU、输出寄存器间的数据通路。控制部分为状态机的状态、reset信号、ALU输出的信号处理后得到的大小关系，如图中3组蓝色线，控制了所有的MUX。 + +![](pic4.png) + +### 总结 + +本次实验成功用组合逻辑实现了ALU，用时序逻辑实现了四个数排序。 \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/report1.pdf" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/report1.pdf" new file mode 100644 index 0000000..f281470 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab1/report1.pdf" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/fifo_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/fifo_simu.v" new file mode 100644 index 0000000..1bf4acc --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/fifo_simu.v" @@ -0,0 +1,85 @@ +`timescale 1ns / 1ps +// fifo simu +// 2020 COD Lab2 +// ustcpetergu + +module fifo_simu(); + reg clk, rst; + reg [7:0]din; + reg en_in; + reg en_out; + wire en_in_in; + wire en_out_in; + wire [7:0]dout; + wire [4:0]count; + + fifo fifo_inst + ( + .clk(clk), + .rst(rst), + .din(din), + .en_in(en_in), + .en_out(en_out), + .en_in_in(en_in_in), + .en_out_in(en_out_in), + .dout(dout), + .count(count) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + rst = 1; + en_in = 0; + en_out = 0; + din = 0; + + #10 + rst = 0; + en_in = 1; + din = 8'hf0; + + #40 + #10 + din = 8'hf1; + + #10 + en_in = 0; + + #40 + #10 + en_in = 1; + din = 8'hff; + + #40 + #10 + en_in = 0; + en_out = 1; + + #40 + #10 + en_in = 1; + en_out = 0; + din = 8'hee; + + #40 + #10 + en_in = 0; + en_out = 1; + + #10 + en_out = 0; + + #10 + en_out = 1; + + #10 + en_out = 0; + + #20 + $finish; + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/mem_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/mem_simu.v" new file mode 100644 index 0000000..bda89fa --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/mem_simu.v" @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +// RAM simu +// 2020 COD Lab2 +// ustcpetergu + +module mem_simu(); + reg clk; + reg en, we; + reg [3:0]addr; + reg [7:0]din; + wire [7:0]dout; + + ram_16x8 ram_16x8_inst + ( + .clk(clk), + .en(en), + .we(we), + .addr(addr), + .din(din), + .dout(dout) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + en = 1; + we = 0; + addr = 4'b1; + din = 8'b0; + + #10 + we = 1; + din = 8'b01111111; + #10 + we = 0; + #10 + addr = 4'b10; + + #20 + $finish; + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/regfile_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/regfile_simu.v" new file mode 100644 index 0000000..8a108a3 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sim_1/new/regfile_simu.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +// regfile simu +// 2020 COD Lab2 +// ustcpetergu + + +module regfile_simu(); + reg clk; + reg [4:0]ra0, ra1; + reg [4:0]wa; + reg we; + reg [31:0]wd; + wire [31:0]rd0, rd1; + + register_file register_file_inst + ( + .clk(clk), + .ra0(ra0), + .ra1(ra1), + .wa(wa), + .we(we), + .wd(wd), + .rd0(rd0), + .rd1(rd1) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + ra0 = 1; + ra1 = 2; + wa = 0; + we = 0; + wd = 0; + + #5 + ra0 = 3; + ra1 = 4; + + #5 + we = 1; + wa = 1; + wd = 32'hff; + + #10 + wa = 2; + wd = 32'hee; + + #10 + we = 0; + ra0 = 1; + ra1 = 2; + + #20 + $finish; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" new file mode 100644 index 0000000..9320ebd --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" @@ -0,0 +1,102 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dist_mem_gen_0 + + + 4 + 0 + 16 + ./ + zynq + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + no_coe_file_loaded + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 8 + dist_mem_gen_0 + 0 + ce_overrides_sync_controls + no_coe_file_loaded + false + false + 8 + 0 + 16 + 16 + non_registered + false + false + non_registered + single_port_ram + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/edgefetcher.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/edgefetcher.v" new file mode 100644 index 0000000..e402c2a --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/edgefetcher.v" @@ -0,0 +1,29 @@ +`timescale 1ns / 1ps +// edgefetcher +// 2020 COD Lab +// ustcpetergu + + +module edgefetcher + ( + input clk, rst, + input y, + output p + ); + reg [1:0]state, next_state; + assign p = (state == 1); + always @ (posedge clk) begin + if (rst) state <= 0; + else state <= next_state; + end + always @ (*) begin + next_state = state; + case (state) + 0: if (y) next_state = 1; + 1: if (y) next_state = 2; else next_state = 0; + 2: if (y) next_state = 2; else next_state = 0; + default: next_state = 0; + endcase + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/fifo.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/fifo.v" new file mode 100644 index 0000000..3251ceb --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/fifo.v" @@ -0,0 +1,88 @@ +`timescale 1ns / 1ps +// fifo +// 2020 COD Lab2 +// ustcpetergu + +module mux21 + #(parameter N = 8) + ( + input [N-1:0]a, + input [N-1:0]b, + input sel, + output reg [N-1:0]o + ); + always @ (*) begin + if (sel == 0) o = a; + else o = b; + end +endmodule + +module fifo + ( + input clk, rst, + input [7:0]din, + input en_in, + input en_out, + output en_in_in, + output en_out_in, + output [7:0]dout, + output reg [4:0]count = 0 + ); + + reg [3:0]head = 4'b0; + reg [3:0]tailp1 = 4'b0; + wire [3:0]head_wire; + wire [3:0]tailp1_wire; + wire [4:0]count_wire; + wire [3:0]head_wire_rst; + wire [3:0]tailp1_wire_rst; + wire [4:0]count_wire_rst; + + wire we; + wire [3:0]a; + dist_mem_gen_0 dist_mem_gen_0_inst ( + .clk(clk), + .we(we), + .a(a), + .d(din), + .spo(dout) + ); + + //wire en_in_in, en_out_in; + edgefetcher edgefetcher_inst_1 ( + .clk(clk), + .rst(rst), + .y(en_in), + .p(en_in_in) + ); + edgefetcher edgefetcher_inst_2 ( + .clk(clk), + .rst(rst), + .y(en_out), + .p(en_out_in) + ); + + wire en_in_real = en_in_in & (count != 5'b11111); + wire en_out_real = en_out_in & (count != 5'b0); + + // we port selection + mux21 #(1) mux21_1 (1'b0, 1'b1, en_in_real, we); + // addr: part it at head if no enqueue + mux21 #(4) mux21_2 (head, tailp1, en_in_real, a); + // tail++,count++ if enqueue, head++,count-- if dequeue + mux21 #(4) mux21_3 (tailp1, tailp1 + 1, en_in_real, tailp1_wire); + mux21 #(4) mux21_3_rst (tailp1_wire, 4'b1, rst, tailp1_wire_rst); + mux21 #(4) mux21_4 (head, head + 1, en_out_real, head_wire); + mux21 #(4) mux21_4_rst (head_wire, 4'b0, rst, head_wire_rst); + wire [4:0]countpm; + mux21 #(5) mux21_5 (count + 1, count - 1, en_out_real, countpm); + mux21 #(5) mux21_6 (count, countpm, en_in_real | en_out_real, count_wire); + mux21 #(5) mux21_6_rst (count_wire, 5'b0, rst, count_wire_rst); + always @ (posedge clk) begin + tailp1 <= tailp1_wire_rst; + head <= head_wire_rst; + count <= count_wire_rst; + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/ram_16x8.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/ram_16x8.v" new file mode 100644 index 0000000..4465ef7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/ram_16x8.v" @@ -0,0 +1,32 @@ +`timescale 1ns / 1ps +// RAM +// 2020 COD Lab2 +// ustcpetergu + +module ram_16x8 + ( + input clk, + input en, we, + input [3:0]addr, // depth: 16 + input [7:0]din, // data width: 8 + output [7:0]dout + ); + + reg [3:0]addr_reg; + reg [7:0]mem[15:0]; + + initial $readmemb("/home/petergu/MyHome/COD/lab2/mem.dat", mem); + + assign dout = mem[addr_reg]; + + always @ (posedge clk) begin + if (en) begin + addr_reg <= addr; + if (we) begin + mem[addr] <= din; + end + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/register_file.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/register_file.v" new file mode 100644 index 0000000..3b76678 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/lab2-regfile-mem-fifo/lab2-regfile-mem-fifo.srcs/sources_1/new/register_file.v" @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +// regfile +// 2020 COD Lab2 +// ustcpetergu + +module register_file + #(parameter WIDTH = 32) + ( + input clk, + input [4:0]ra0, + input [4:0]ra1, + input [4:0]wa, + input we, + input [WIDTH-1:0]wd, + output reg [WIDTH-1:0]rd0, + output reg [WIDTH-1:0]rd1 + ); + + reg [WIDTH-1:0]regfile[31:0]; + initial $readmemh("/home/petergu/MyHome/COD/lab2/regfile.dat", regfile); + + always @ (*) begin + if (ra0 == 5'b0) rd0 = 0; + else rd0 = regfile[ra0]; + if (ra1 == 5'b0) rd1 = 0; + else rd1 = regfile[ra1]; + end + + always @ (posedge clk) begin + if (we) begin + if (wa != 5'b0) begin + regfile[wa] <= wd; + end + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/mem.dat" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/mem.dat" new file mode 100644 index 0000000..f675484 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/mem.dat" @@ -0,0 +1,5 @@ +01000000 +01000001 +01000010 +01000011 +01000100 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic1.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic1.png" new file mode 100644 index 0000000..749f535 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic1.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic2.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic2.png" new file mode 100644 index 0000000..871cb83 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic2.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic3.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic3.png" new file mode 100644 index 0000000..b7e5242 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/pic3.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/regfile.dat" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/regfile.dat" new file mode 100644 index 0000000..987bac9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/regfile.dat" @@ -0,0 +1,32 @@ +0000f000 +0000f001 +0000f002 +0000f003 +0000f004 +0000f005 +0000f006 +0000f007 +0000f008 +0000f009 +0000f00a +0000f00b +0000f00c +0000f00d +0000f00e +0000f00f +0000f010 +0000f011 +0000f012 +0000f013 +0000f014 +0000f015 +0000f016 +0000f017 +0000f018 +0000f019 +0000f01a +0000f01b +0000f01c +0000f01d +0000f01e +0000f01f diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/report.md" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/report.md" new file mode 100644 index 0000000..50dc572 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab2/report.md" @@ -0,0 +1,407 @@ +## Lab2 Regfile&RAM&FIFO + +古宜民 PB17000002 + +2020.5.3 + +### Register File + +通过组合逻辑实现两个异步读取，时序逻辑实现一个同步写入。使用 `reg []regfile[]` 实现“二维数组“寄存器。 + +代码： + +```verilog +module register_file + #(parameter WIDTH = 32) + ( + input clk, + input [4:0]ra0, + input [4:0]ra1, + input [4:0]wa, + input we, + input [WIDTH-1:0]wd, + output reg [WIDTH-1:0]rd0, + output reg [WIDTH-1:0]rd1 + ); + + reg [WIDTH-1:0]regfile[31:0]; + initial $readmemh("/home/petergu/MyHome/COD/lab2/regfile.dat", regfile); + + always @ (*) begin + if (ra0 == 5'b0) rd0 = 0; + else rd0 = regfile[ra0]; + if (ra1 == 5'b0) rd1 = 0; + else rd1 = regfile[ra1]; + end + + always @ (posedge clk) begin + if (we) begin + if (wa != 5'b0) begin + regfile[wa] <= wd; + end + end + end + +endmodule +``` + +仿真： + +```verilog +module regfile_simu(); + reg clk; + reg [4:0]ra0, ra1; + reg [4:0]wa; + reg we; + reg [31:0]wd; + wire [31:0]rd0, rd1; + + register_file register_file_inst + ( + .clk(clk), + .ra0(ra0), + .ra1(ra1), + .wa(wa), + .we(we), + .wd(wd), + .rd0(rd0), + .rd1(rd1) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + ra0 = 1; + ra1 = 2; + wa = 0; + we = 0; + wd = 0; + + #5 + ra0 = 3; + ra1 = 4; + + #5 + we = 1; + wa = 1; + wd = 32'hff; + + #10 + wa = 2; + wd = 32'hee; + + #10 + we = 0; + ra0 = 1; + ra1 = 2; + + #20 + $finish; + end +endmodule +``` + +仿真结果： + +![](pic1.png) + +寄存器堆初始值为f001,f002,....，在第2，3个周期中对1，2地址写入00ff和00ee，之后异步同时读取1，2地址处的值，可见值已经变为00ff和00ee了。 + +### RAM 8x16 + +8x16大小的RAM地址线4位，数据线8位。同步读写，用readmemb初始化。 + +```verilog +module ram_16x8 + ( + input clk, + input en, we, + input [3:0]addr, // depth: 16 + input [7:0]din, // data width: 8 + output [7:0]dout + ); + + reg [3:0]addr_reg; + reg [7:0]mem[15:0]; + + initial $readmemb("/home/petergu/MyHome/COD/lab2/mem.dat", mem); + + assign dout = mem[addr_reg]; + + always @ (posedge clk) begin + if (en) begin + addr_reg <= addr; + if (we) begin + mem[addr] <= din; + end + end + end +endmodule + +``` + +仿真： + +```verilog +module mem_simu(); + reg clk; + reg en, we; + reg [3:0]addr; + reg [7:0]din; + wire [7:0]dout; + + ram_16x8 ram_16x8_inst + ( + .clk(clk), + .en(en), + .we(we), + .addr(addr), + .din(din), + .dout(dout) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + en = 1; + we = 0; + addr = 4'b1; + din = 8'b0; + + #10 + we = 1; + din = 8'b01111111; + #10 + we = 0; + #10 + addr = 4'b10; + + #20 + $finish; + end +endmodule +``` + +仿真结果： + +![](pic2.png) + +地址1，2处的初始化值为41，42. 第一个周期读地址1处的值，第二个周期向1处写入值7f，第三个周期读，可见地址1处值变为了7f. 第四个周期读地址2处的值，为42. + +### FIFO + +先进先出队列，en_in和en_out经过取边沿后控制进出队列。使用head和tailp1(tail+1)头尾指针控制循环队列，如果入队且队列不满，就向tailp1处写入入队值，然后tailp1加1. 如果出队，读出head处的值，head加一。使用一块分布式RAM作为存储。 + +使用了结构化描述方法，为此实现了mux21选择器和edgefetcher取边沿电路。 + +```verilog +module mux21 + #(parameter N = 8) + ( + input [N-1:0]a, + input [N-1:0]b, + input sel, + output reg [N-1:0]o + ); + always @ (*) begin + if (sel == 0) o = a; + else o = b; + end +endmodule + +module edgefetcher + ( + input clk, rst, + input y, + output p + ); + reg [1:0]state, next_state; + assign p = (state == 1); + always @ (posedge clk) begin + if (rst) state <= 0; + else state <= next_state; + end + always @ (*) begin + next_state = state; + case (state) + 0: if (y) next_state = 1; + 1: if (y) next_state = 2; else next_state = 0; + 2: if (y) next_state = 2; else next_state = 0; + default: next_state = 0; + endcase + end +endmodule + +module fifo + ( + input clk, rst, + input [7:0]din, + input en_in, + input en_out, + output en_in_in, + output en_out_in, + output [7:0]dout, + output reg [4:0]count = 0 + ); + + reg [3:0]head = 4'b0; + reg [3:0]tailp1 = 4'b0; + wire [3:0]head_wire; + wire [3:0]tailp1_wire; + wire [4:0]count_wire; + wire [3:0]head_wire_rst; + wire [3:0]tailp1_wire_rst; + wire [4:0]count_wire_rst; + + wire we; + wire [3:0]a; + dist_mem_gen_0 dist_mem_gen_0_inst ( + .clk(clk), + .we(we), + .a(a), + .d(din), + .spo(dout) + ); + + //wire en_in_in, en_out_in; + edgefetcher edgefetcher_inst_1 ( + .clk(clk), + .rst(rst), + .y(en_in), + .p(en_in_in) + ); + edgefetcher edgefetcher_inst_2 ( + .clk(clk), + .rst(rst), + .y(en_out), + .p(en_out_in) + ); + + wire en_in_real = en_in_in & (count != 5'b11111); + wire en_out_real = en_out_in & (count != 5'b0); + + // we port selection + mux21 #(1) mux21_1 (1'b0, 1'b1, en_in_real, we); + // addr: part it at head if no enqueue + mux21 #(4) mux21_2 (head, tailp1, en_in_real, a); + // tail++,count++ if enqueue, head++,count-- if dequeue + mux21 #(4) mux21_3 (tailp1, tailp1 + 1, en_in_real, tailp1_wire); + mux21 #(4) mux21_3_rst (tailp1_wire, 4'b1, rst, tailp1_wire_rst); + mux21 #(4) mux21_4 (head, head + 1, en_out_real, head_wire); + mux21 #(4) mux21_4_rst (head_wire, 4'b0, rst, head_wire_rst); + wire [4:0]countpm; + mux21 #(5) mux21_5 (count + 1, count - 1, en_out_real, countpm); + mux21 #(5) mux21_6 (count, countpm, en_in_real | en_out_real, count_wire); + mux21 #(5) mux21_6_rst (count_wire, 5'b0, rst, count_wire_rst); + always @ (posedge clk) begin + tailp1 <= tailp1_wire_rst; + head <= head_wire_rst; + count <= count_wire_rst; + end + +endmodule +``` + +仿真： + +```verilog +module fifo_simu(); + reg clk, rst; + reg [7:0]din; + reg en_in; + reg en_out; + wire en_in_in; + wire en_out_in; + wire [7:0]dout; + wire [4:0]count; + + fifo fifo_inst + ( + .clk(clk), + .rst(rst), + .din(din), + .en_in(en_in), + .en_out(en_out), + .en_in_in(en_in_in), + .en_out_in(en_out_in), + .dout(dout), + .count(count) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + rst = 1; + en_in = 0; + en_out = 0; + din = 0; + + #10 + rst = 0; + en_in = 1; + din = 8'hf0; + + #40 + #10 + din = 8'hf1; + + #10 + en_in = 0; + + #40 + #10 + en_in = 1; + din = 8'hff; + + #40 + #10 + en_in = 0; + en_out = 1; + + #40 + #10 + en_in = 1; + en_out = 0; + din = 8'hee; + + #40 + #10 + en_in = 0; + en_out = 1; + + #10 + en_out = 0; + + #10 + en_out = 1; + + #10 + en_out = 0; + + #20 + $finish; + end +endmodule +``` + +仿真结果： + +![](pic3.png) + +如图，从左到右依次入队f0、ff、出队（f0）、入队ee、出队（ff）、出队（ee）。 + +其中en_in_in和en_out_in为取边沿之后的输入信号，count为队列中元素个数。 + +### 总结 + +本次实验实现了Regfile、RAM和FIFO，内容主要是对寄存器和内存的读写操作。 + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/instr_ram.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/instr_ram.coe" new file mode 100644 index 0000000..8751190 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/instr_ram.coe" @@ -0,0 +1,6 @@ +memory_initialization_radix=16; +memory_initialization_vector= +5 +8 +a +; diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/instr_rom.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/instr_rom.coe" new file mode 100644 index 0000000..9b801ba --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/instr_rom.coe" @@ -0,0 +1,24 @@ +memory_initialization_radix=2; +memory_initialization_vector= + 10001100000000010000000000000000, + 10001100000000100000000000000001, + 00100000001000110000000000001001, + 00000000001000100010000000100000, + 10101100000001000000000000000011, + 10001100000001010000000000000011, + 00010000011001000000000000000001, + 00010000001000010000000000000001, + 00001000000000000000000000001000, + 00001000000000000000000000001001, + 0; +; 0 lw $1, $0(0x0) +; 4 lw $2, $0(0x1) +; 8 addi $3, $1, 9 +; 12 add $4, $1, $2 +; 16 sw $4, $0(0x3) +; 20 lw $5, $0(0x3) +; 24 beq $3, $4, +1 +; 28 beq $1, $1, +1 +; 32 j 32 +; 36 j 36 + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/cpu-single-cyc-simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/cpu-single-cyc-simu.v" new file mode 100644 index 0000000..0d1aa36 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/cpu-single-cyc-simu.v" @@ -0,0 +1,99 @@ +`timescale 1ns / 1ps +// single cycle CPU simu +// 2020 COD Lab3 +// ustcpetergu + + +module cpu_single_cyc_simu(); + reg clk; + reg rst; + reg run; + + reg [7:0]m_rf_addr; + + wire RegDst; + wire Jump; + wire Branch; + wire MemRead; + wire MemtoReg; + wire [2:0]ALUOp; + wire MemWrite; + wire ALUSrc; + wire RegWrite; + + wire [31:0] pc; + wire [31:0] newpc; + wire [31:0] instruction; + + wire [31:0]ReadData1; + wire [31:0]ReadData2; + wire [31:0]ReadData_ram; + + wire [31:0]ALUResult; + wire Zero; + + wire [31:0]rf_data; + wire [31:0]m_data; + + wire [31:0]imm; + wire [31:0]alu_b; + wire run_real; + cpu_single_cyc cpu_single_cyc_inst + ( + .clk(clk), + .rst(rst), + .run_in(run), + .RegDst(RegDst), + .Jump(Jump), + .Branch(Branch), + .MemRead(MemRead), + .MemtoReg(MemtoReg), + .ALUOp(ALUOp), + .MemWrite(MemWrite), + .ALUSrc(ALUSrc), + .RegWrite(RegWrite), + .pc(pc), + .newpc(newpc), + .instruction(instruction), + .ReadData1(ReadData1), + .ReadData2(ReadData2), + .ReadData_ram(ReadData_ram), + .ALUResult(ALUResult), + .Zero(Zero), + .m_rf_addr(m_rf_addr), + .rf_data(rf_data), + .m_data(m_data), + .imm(imm), + .alu_b(alu_b), + .run(run_real) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + rst = 1; + run = 1; + m_rf_addr = 8'b0; + + #10 + rst = 0; + #75 + run = 0; + #11 + run = 1; + #10 + run = 0; + #19 + run = 1; + #25 + rst = 1; + #10 + rst = 0; + #100 + $finish; + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/debug-unit-simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/debug-unit-simu.v" new file mode 100644 index 0000000..3822bd9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/debug-unit-simu.v" @@ -0,0 +1,105 @@ +`timescale 1ns / 1ps +// single cycle CPU DBU simu +// 2020 COD Lab3 +// ustcpetergu + +module debug_unit_simu(); + reg clk, rst; + + reg succ; + reg step; + reg [2:0]sel; + reg m_rf; + reg inc; + reg dec; + wire [15:0]led; + wire an; + wire seg; + wire [31:0]seg_data; + debug_unit debug_unit_inst + ( + .clk(clk), + .rst(rst), + .succ(succ), + .step(step), + .sel(sel), + .m_rf(m_rf), + .inc(inc), + .dec(dec), + + .led(led), + .an(an), + .seg(seg), + + .seg_data(seg_data) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + rst = 0; + + #10 + rst = 1; + succ = 0; + step = 0; + sel = 1; + m_rf = 0; + inc = 0; + dec = 0; + + #10 + rst = 0; + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + + #50 + sel = 2; + #10 + sel = 3; + #10 + sel = 4; + #10 + sel = 5; + #10 + sel = 6; + #10 + sel = 7; + + //#10 + //step = 1; + //#30 + //step = 0; + + #10 + sel = 0; + inc = 1; + #10 + inc = 0; + #10 + inc = 1; + #10 + inc = 0; + + #30 + m_rf = 1; + dec = 1; + #10 + dec = 0; + #10 + dec = 1; + #10 + dec = 0; + + #40 + $finish; + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" new file mode 100644 index 0000000..f20ca8b --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" @@ -0,0 +1,39 @@ + + + xilinx.com + xci + unknown + 1.0 + + + alu_0 + + + 32 + alu_0 + 32 + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" new file mode 100644 index 0000000..0ce36e2 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" @@ -0,0 +1,44 @@ + + + xilinx.com + xci + unknown + 1.0 + + + edgefetcher_0 + + + + + 100000000 + 0 + 0.000 + 0 + ACTIVE_LOW + edgefetcher_0 + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/ram_data/ram_data.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/ram_data/ram_data.xci" new file mode 100644 index 0000000..ef4cd96 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/ram_data/ram_data.xci" @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ram_data + + + 8 + 11111111111111111111111111111111 + 256 + ./ + zynq + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + ram_data.mif + 2 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 32 + ram_data + 0 + ce_overrides_sync_controls + ../../../../../instr_ram.coe + false + false + 32 + ffffffff + 16 + 256 + non_registered + false + false + non_registered + dual_port_ram + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/rom_instr/rom_instr.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/rom_instr/rom_instr.xci" new file mode 100644 index 0000000..0119238 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/rom_instr/rom_instr.xci" @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + rom_instr + + + 8 + 11101110 + 256 + ./ + zynq + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + rom_instr.mif + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 32 + rom_instr + 0 + ce_overrides_sync_controls + ../../../../../instr_rom.coe + false + false + 32 + ee + 16 + 256 + non_registered + false + false + non_registered + rom + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/cpu-single-cyc.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/cpu-single-cyc.v" new file mode 100644 index 0000000..323f335 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/cpu-single-cyc.v" @@ -0,0 +1,165 @@ +`timescale 1ns / 1ps +// single cycle CPU +// 2020 COD Lab3 +// ustcpetergu + +module cpu_single_cyc + ( + input clk, + input rst, + input run_in, + + output reg RegDst, + output reg Jump, + output reg Branch, + output reg MemRead, + output reg MemtoReg, + output reg [2:0]ALUOp, + output reg MemWrite, + output reg ALUSrc, + output reg RegWrite, + + output reg [31:0] pc, + output reg [31:0] newpc, + output wire [31:0] instruction, + + output wire [31:0]ReadData1, + output wire [31:0]ReadData2, + output wire [31:0]ReadData_ram, + + output wire [31:0]ALUResult, + output wire Zero, + + + // debug + input [7:0]m_rf_addr, + output wire [31:0]rf_data, + output wire [31:0]m_data, + + // temporary debug + output wire [31:0]imm, + output reg [31:0]alu_b, + output reg run + ); + + assign imm = {{16{instruction[15]}}, instruction[15:0]}; + + rom_instr rom_instr_inst + ( + .a(pc[9:2]), + .spo(instruction) + ); + + reg [4:0]WriteRegister; + reg [31:0]WriteData_alu; + register_file register_file_inst + ( + .clk(clk), + .ra0(instruction[25:21]), + .ra1(instruction[20:16]), + .ra2(m_rf_addr), + .wa(WriteRegister), + .we(RegWrite), + .wd(WriteData_alu), + .rd0(ReadData1), + .rd1(ReadData2), + .rd2(rf_data) + ); + + ram_data ram_data_inst + ( + .clk(clk), + .we(MemWrite), + .a(ALUResult[7:0]), + .d(ReadData2), + .dpra(m_rf_addr), + .spo(ReadData_ram), + .dpo(m_data) + ); + + alu_0 alu_0_inst + ( + .m(ALUOp), + .a(ReadData1), + .b(alu_b), + .y(ALUResult), + .zf(Zero) + //.cf(), + //.of() + ); + + always @(*) begin + if (RegDst == 1'b1) WriteRegister = instruction[15:11]; + else WriteRegister = instruction[20:16]; + + if (ALUSrc == 1'b1) alu_b = imm; + else alu_b = ReadData2; + + if (MemtoReg == 1'b1) WriteData_alu = ReadData_ram; + else WriteData_alu = ALUResult; + end + + always @ (*) begin + if (run) begin + RegDst = 0; + Jump = 0; + Branch = 0; + MemRead = 0; + MemtoReg = 0; + MemWrite = 0; + ALUSrc = 0; + RegWrite = 0; + ALUOp = 3'b000; // default: plus + case (instruction[31:26]) + 6'b000000: + case (instruction[5:0]) + // add--- --rs- --rt- --rd- shamt funct- + 6'b100000: begin RegDst = 1; RegWrite = 1; end + default: ; + endcase + // addi-- --rs- --rt- ----immediate--- + 6'b001000: begin ALUSrc = 1; RegWrite = 1; end + // lw---- --rs- --rt- ----addr-------- + 6'b100011: begin ALUSrc = 1; RegWrite = 1; MemRead = 1; MemtoReg = 1; end + // sw---- --rs- --rt- ----addr-------- + 6'b101011: begin ALUSrc = 1; MemWrite = 1; end + // beq-- --rs- --rt- ----addr-------- + 6'b000100: begin Branch = 1; ALUOp = 3'b001; end + // j---- ----addr------------------ + 6'b000010: begin Jump = 1; end + default: ; + endcase + + if (Jump == 1'b0) begin + if ((Branch & Zero) == 1'b0) newpc = pc + 4; + else newpc = pc + 4 + (imm << 2); + end + else newpc = {4'b0000, instruction[25:0], 2'b00}; + //else newpc = {{pc + 4}[31:28], instruction[25:0], 2'b00}; + end + else begin + RegDst = 0; + Jump = 0; + Branch = 0; + MemRead = 0; + MemtoReg = 0; + MemWrite = 0; + ALUSrc = 0; + RegWrite = 0; + ALUOp = 3'b000; + newpc = pc; + end + end + + always @ (posedge clk) begin + if (rst) begin + pc <= 32'b0; + run <= 0; + end + else begin + pc <= newpc; + run <= run_in; + end + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/debug-unit.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/debug-unit.v" new file mode 100644 index 0000000..70af960 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/debug-unit.v" @@ -0,0 +1,238 @@ +`timescale 1ns / 1ps +// single cycle CPU -- debug unit +// 2020 COD Lab3 +// ustcpetergu + +// 7-segment digital control +module seven_segment + ( + input clk, + input rst, + input [31:0]x, + output reg [7:0]an, + output reg [6:0]seg + ); + reg [31:0]count = 0; + localparam UPDATE_COUNT = 100000; + reg [2:0]select = 0; + reg [3:0]x0; + always @ (*) begin + case (select) + 0: begin x0 = x[3:0]; an = 8'b11111110; end + 1: begin x0 = x[7:4]; an = 8'b11111101; end + 2: begin x0 = x[11:8]; an = 8'b11111011; end + 3: begin x0 = x[15:12]; an = 8'b11110111; end + 4: begin x0 = x[19:16]; an = 8'b11101111; end + 5: begin x0 = x[23:20]; an = 8'b11011111; end + 6: begin x0 = x[27:24]; an = 8'b10111111; end + 7: begin x0 = x[31:28]; an = 8'b01111111; end + default: begin x0 = 0; an = 0; end + endcase + case (x0) + // +7+ + // 2 6 + // +1+ + // 3 5 + // +4+ + 0: seg = 7'b1000000; + 1: seg = 7'b1111001; + 2: seg = 7'b0100100; + 3: seg = 7'b0110000; + 4: seg = 7'b0011001; + 5: seg = 7'b0010010; + 6: seg = 7'b0000010; + 7: seg = 7'b1111000; + 8: seg = 7'b0000000; + 9: seg = 7'b0010000; + 10: seg = 7'b0001000; + 11: seg = 7'b0000011; + 12: seg = 7'b1000110; + 13: seg = 7'b0100001; + 14: seg = 7'b0000110; + 15: seg = 7'b0001110; + default: seg = 0; + endcase + end + always @ (posedge clk) begin + if (rst) + count <= 0; + else if (count >= UPDATE_COUNT) begin + count <= 0; + select <= select + 1; + end else + count <= count + 1; + end +endmodule + +module debug_unit + ( + // from human input + input clk, + input rst,//BTNL + input succ, // SW15 + input step, // BTNC + input [2:0]sel, // SW2~SW0 + input m_rf, // SW3 + input inc, // BTNU + input dec, // BTND + + // to human visible device + output reg [15:0]led = 0, + output wire [7:0]an, + output wire [6:0]seg, + + output reg [31:0]seg_data = 0 + ); + + seven_segment seven_segment_inst + ( + .clk(clk), + .rst(rst), + .x(seg_data), + .an(an), + .seg(seg) + ); + + reg run = 0; + reg after_run = 0; + reg [7:0]m_rf_addr = 0; + + wire step_real; + wire inc_real; + wire dec_real; + + edgefetcher_0 edgefetcher_inst_0 + ( + .clk(clk), + .rst(rst), + .y(step), + .p(step_real) + ); + edgefetcher_0 edgefetcher_inst_1 + ( + .clk(clk), + .rst(rst), + .y(inc), + .p(inc_real) + ); + edgefetcher_0 edgefetcher_inst_2 + ( + .clk(clk), + .rst(rst), + .y(dec), + .p(dec_real) + ); + + // from CPU + wire RegDst; + wire Jump; + wire Branch; + wire MemRead; + wire MemtoReg; + wire [2:0]ALUOp; + wire MemWrite; + wire ALUSrc; + wire RegWrite; + + wire [31:0]pc; + wire [31:0]newpc; + wire [31:0]instruction; + + wire [31:0]ReadData1; + wire [31:0]ReadData2; + wire [31:0]ReadData_ram; + + wire [31:0]ALUResult; + wire Zero; + + wire [31:0]rf_data; + wire [31:0]m_data; + // saved signals + reg RegDst_save; + reg Jump_save; + reg Branch_save; + reg MemRead_save; + reg MemtoReg_save; + reg [2:0]ALUOp_save; + reg MemWrite_save; + reg ALUSrc_save; + reg RegWrite_save; + + reg [31:0] pc_save; + reg [31:0] newpc_save; + reg [31:0] instruction_save; + + reg [31:0]ReadData1_save; + reg [31:0]ReadData2_save; + reg [31:0]ReadData_ram_save; + + reg [31:0]ALUResult_save; + reg Zero_save; + + // m_data and rf_data don't need save + //reg [31:0]rf_data_save; + //reg [31:0]m_data_save; + cpu_single_cyc cpu_single_cyc_inst + ( + .clk(clk), + .rst(rst), + .run_in(run), + .RegDst(RegDst), + .Jump(Jump), + .Branch(Branch), + .MemRead(MemRead), + .MemtoReg(MemtoReg), + .ALUOp(ALUOp), + .MemWrite(MemWrite), + .ALUSrc(ALUSrc), + .RegWrite(RegWrite), + .pc(pc), + .newpc(newpc), + .instruction(instruction), + .ReadData1(ReadData1), + .ReadData2(ReadData2), + .ALUResult(ALUResult), + .Zero(Zero), + .ReadData_ram(ReadData_ram), + .m_rf_addr(m_rf_addr), + .rf_data(rf_data), + .m_data(m_data) + ); + + always @ (posedge clk) begin + if (rst) begin + m_rf_addr <= 0; + run <= 0; + after_run <= 0; + led <= 16'b0; + {RegDst_save, Jump_save, Branch_save, MemRead_save, MemtoReg_save, ALUOp_save, MemWrite_save, ALUSrc_save, RegWrite_save, pc_save, newpc_save, instruction_save, ReadData1_save, ReadData2_save, ReadData_ram_save, ALUResult_save, Zero_save} <= 236'b0; + end + else begin + if (after_run) {RegDst_save, Jump_save, Branch_save, MemRead_save, MemtoReg_save, ALUOp_save, MemWrite_save, ALUSrc_save, RegWrite_save, pc_save, newpc_save, instruction_save, ReadData1_save, ReadData2_save, ReadData_ram_save, ALUResult_save, Zero_save} <= {RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, pc, newpc, instruction, ReadData1, ReadData2, ReadData_ram, ALUResult, Zero}; + + if (inc_real) m_rf_addr <= m_rf_addr + 1; + else if (dec_real) m_rf_addr <= m_rf_addr - 1; + + run <= step_real; + after_run <= run; + if (sel == 3'b0) + led <= {8'b0, m_rf_addr}; + else + led <= {4'b0, Jump_save, Branch_save, RegDst_save, RegWrite_save, MemRead_save, MemtoReg_save, MemWrite_save, ALUOp_save, ALUSrc_save, Zero_save}; + case (sel) + 0: begin + if (m_rf == 1) seg_data <= m_data; else seg_data = rf_data; + end + 1: seg_data <= newpc_save; + 2: seg_data <= pc_save; + 3: seg_data <= instruction_save; + 4: seg_data <= ReadData1_save; + 5: seg_data <= ReadData2_save; + 6: seg_data <= ALUResult_save; + 7: seg_data <= ReadData_ram_save; + default: seg_data <= 32'b0; + endcase + end + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/register_file.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/register_file.v" new file mode 100644 index 0000000..a39e064 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/register_file.v" @@ -0,0 +1,42 @@ +`timescale 1ns / 1ps +// regfile with debug port +// 2020 COD Lab3 +// ustcpetergu + +module register_file + #(parameter WIDTH = 32) + ( + input clk, + input [4:0]ra0, + input [4:0]ra1, + input [4:0]ra2, + input [4:0]wa, + input we, + input [WIDTH-1:0]wd, + output reg [WIDTH-1:0]rd0, + output reg [WIDTH-1:0]rd1, + output reg [WIDTH-1:0]rd2 + ); + + reg [WIDTH-1:0]regfile[31:0]; + initial $readmemh("/home/petergu/MyHome/COD/lab3/regfile.dat", regfile); + + always @ (*) begin + if (ra0 == 5'b0) rd0 = 0; + else rd0 = regfile[ra0]; + if (ra1 == 5'b0) rd1 = 0; + else rd1 = regfile[ra1]; + if (ra2 == 5'b0) rd2 = 0; + else rd2 = regfile[ra2]; + end + + always @ (posedge clk) begin + if (we) begin + if (wa != 5'b0) begin + regfile[wa] <= wd; + end + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3.tcl" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3.tcl" new file mode 100644 index 0000000..32dc900 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/lab3.tcl" @@ -0,0 +1,613 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1 (64-bit) +# +# lab3.tcl: Tcl script for re-creating project 'lab3-cpu-single-cycle' +# +# Generated by Vivado on Wed May 13 19:37:50 CST 2020 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (lab3.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/cpu-single-cyc.v" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/register_file.v" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/debug-unit.v" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/rom_instr/rom_instr.xci" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/ram_data/ram_data.xci" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/debug-unit-simu.v" +# "/home/petergu/MyHome/COD/lab3/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/cpu-single-cyc-simu.v" +# +# 3. The following remote source files that were added to the original project:- +# +# "/home/petergu/MyHome/COD/lab3/instr_rom.coe" +# "/home/petergu/MyHome/COD/lab3/instr_ram.coe" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "lab3-cpu-single-cycle" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "lab3.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/lab3-cpu-single-cycle"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "www.digilentinc.com:pynq-z1:part0:1.0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "pynq-z1" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "20" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "20" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "20" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "20" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "20" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "20" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "1" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "20" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "94" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/instr_rom.coe"] \ + [file normalize "${origin_dir}/instr_ram.coe"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/cpu-single-cyc.v" ]\ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/register_file.v" ]\ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/new/debug-unit.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "debug_unit" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/rom_instr/rom_instr.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "rom_instr/rom_instr.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/ram_data/ram_data.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "ram_data/ram_data.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "alu_0/alu_0.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "edgefetcher_0/edgefetcher_0.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/debug-unit-simu.v" ]\ + [file normalize "${origin_dir}/lab3-cpu-single-cycle/lab3-cpu-single-cycle.srcs/sim_1/new/cpu-single-cyc-simu.v" ]\ +] +set imported_files [import_files -fileset sim_1 $files] + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "debug_unit_simu" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "xsim.simulate.log_all_signals" -value "1" -objects $obj +set_property -name "xsim.simulate.saif_all_signals" -value "1" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/logic.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/logic.png" new file mode 100644 index 0000000..d74facc Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/logic.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/pic1.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/pic1.png" new file mode 100644 index 0000000..a78a95c Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/pic1.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/pic2.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/pic2.png" new file mode 100644 index 0000000..3f05b06 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/pic2.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/ram.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/ram.png" new file mode 100644 index 0000000..6d212fd Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/ram.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/regfile.dat" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/regfile.dat" new file mode 100644 index 0000000..987bac9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/regfile.dat" @@ -0,0 +1,32 @@ +0000f000 +0000f001 +0000f002 +0000f003 +0000f004 +0000f005 +0000f006 +0000f007 +0000f008 +0000f009 +0000f00a +0000f00b +0000f00c +0000f00d +0000f00e +0000f00f +0000f010 +0000f011 +0000f012 +0000f013 +0000f014 +0000f015 +0000f016 +0000f017 +0000f018 +0000f019 +0000f01a +0000f01b +0000f01c +0000f01d +0000f01e +0000f01f diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/report.md" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/report.md" new file mode 100644 index 0000000..0d16962 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab3/report.md" @@ -0,0 +1,165 @@ +## Lab3 单周期CPU + +古宜民 PB17000002 + +2020.5.22 + +### CPU + +数据通路和状态设计 + +数据通路为文档上的逻辑图： + +![](logic.png) + +其中指令寄存器处，接入地址为`pc[9:2]`。 + +如果在运行状态，则每个周期时钟上升沿`pc <= newpc`，更新PC的值。在下一个时钟上升沿会写入前一个周期对寄存器堆和数据内存的写入操作。这也是唯一的时序部分，其他的控制器、MUX和读取数据均只需要组合逻辑：只需要对指令的类型和寄存器/立即数/内存地址解码并相应改变各个数据线上的值即可。 + +主要代码： + +WriteRegister，ALU，WriteData三个MUX： + +```verilog + always @(*) begin + if (RegDst == 1'b1) WriteRegister = instruction[15:11]; + else WriteRegister = instruction[20:16]; + + if (ALUSrc == 1'b1) alu_b = imm; + else alu_b = ReadData2; + + if (MemtoReg == 1'b1) WriteData_alu = ReadData_ram; + else WriteData_alu = ALUResult; + end +``` + +控制器Controller的信号： + +```verilog + always @ (*) begin + if (run) begin + RegDst = 0; + Jump = 0; + Branch = 0; + MemRead = 0; + MemtoReg = 0; + MemWrite = 0; + ALUSrc = 0; + RegWrite = 0; + ALUOp = 3'b000; // default: plus + case (instruction[31:26]) + 6'b000000: + case (instruction[5:0]) + // add--- --rs- --rt- --rd- shamt funct- + 6'b100000: begin RegDst = 1; RegWrite = 1; end + default: ; + endcase + // addi-- --rs- --rt- ----immediate--- + 6'b001000: begin ALUSrc = 1; RegWrite = 1; end + // lw---- --rs- --rt- ----addr-------- + 6'b100011: begin ALUSrc = 1; RegWrite = 1; MemRead = 1; MemtoReg = 1; end + // sw---- --rs- --rt- ----addr-------- + 6'b101011: begin ALUSrc = 1; MemWrite = 1; end + // beq-- --rs- --rt- ----addr-------- + 6'b000100: begin Branch = 1; ALUOp = 3'b001; end + // j---- ----addr------------------ + 6'b000010: begin Jump = 1; end + default: ; + endcase + + if (Jump == 1'b0) begin + if ((Branch & Zero) == 1'b0) newpc = pc + 4; + else newpc = pc + 4 + (imm << 2); + end + else newpc = {4'b0000, instruction[25:0], 2'b00}; + end + else begin + RegDst = 0; + Jump = 0; + Branch = 0; + MemRead = 0; + MemtoReg = 0; + MemWrite = 0; + ALUSrc = 0; + RegWrite = 0; + ALUOp = 3'b000; + newpc = pc; + end + end +``` + +时序控制： + +```verilog + always @ (posedge clk) begin + if (rst) begin + pc <= 32'b0; + run <= 0; + end + else begin + pc <= newpc; + run <= run_in; + end + end +``` + +这里为了避免不必要的顺序，三个MUX和Controller写在了两段中。而控制PC的MUX由newpc处的if判断行为级实现了（其实所有代码都是行为级的）。为了和DBU合作，CPU中加入了run信号，run=1时才会继续运行。 + +仿真结果 + +ROM和RAM的初始值如下，使用自编的测试代码，涵盖了全部6条指令。正确运行的结果应为在24 beq处，\$3==5+9=13, \$4==5+8=13, 二者不下相等，不跳转，而28 beq跳转，到36 j 36，开始死循环。 + +![](ram.png) + +![](pic1.png) + +仿真结果可见（标注的部分），依次进行了读取5、读取8、5+9=14、5+8=13、存13、取13、14-13=1不跳转、5-5=0跳转、jump跳转。在中间run暂停以及reset后PC再次置为0后都能得到正确的结果。 + +### DBU + +DBU的目的是控制CPU的运行并从中获得调试数据。而如果在CPU暂停的时候CPU中的控制信号不归零，即使控制了PC不变，也可能出现意外写入，所以控制信号在暂停时必须归0. 从而如果DBU要保持CPU中的信号并显示在数码管和LED上，必须由内部寄存器保存数据。同时手动输入DBU的信号需要进行取边沿。这都导致了从CPU信号出现到显示在人类可阅读设备中需要几个周期的延迟。 + +仿真结果： + +![](pic2.png) + +图为CPU运行2个周期后查看各个信号的值，演示了读取信号和寄存器、内存地址的功能。 + +主要代码： + +```verilog + else begin + if (after_run) {RegDst_save, Jump_save, Branch_save, MemRead_save, MemtoReg_save, ALUOp_save, MemWrite_save, ALUSrc_save, RegWrite_save, pc_save, newpc_save, instruction_save, ReadData1_save, ReadData2_save, ReadData_ram_save, ALUResult_save, Zero_save} <= {RegDst, Jump, Branch, MemRead, MemtoReg, ALUOp, MemWrite, ALUSrc, RegWrite, pc, newpc, instruction, ReadData1, ReadData2, ReadData_ram, ALUResult, Zero}; + + if (inc_real) m_rf_addr <= m_rf_addr + 1; + else if (dec_real) m_rf_addr <= m_rf_addr - 1; + + run <= step_real; + after_run <= run; + if (sel == 3'b0) + led <= {8'b0, m_rf_addr}; + else + led <= {4'b0, Jump_save, Branch_save, RegDst_save, RegWrite_save, MemRead_save, MemtoReg_save, MemWrite_save, ALUOp_save, ALUSrc_save, Zero_save}; + case (sel) + 0: begin + if (m_rf == 1) seg_data <= m_data; else seg_data = rf_data; + end + 1: seg_data <= newpc_save; + 2: seg_data <= pc_save; + 3: seg_data <= instruction_save; + 4: seg_data <= ReadData1_save; + 5: seg_data <= ReadData2_save; + 6: seg_data <= ALUResult_save; + 7: seg_data <= ReadData_ram_save; + default: seg_data <= 32'b0; + endcase + end +``` + +### 总结 + +本次实验实现了单周期CPU，其中其实DBU的实现更加复杂和繁琐一些。刚开始不太熟悉整体运行的逻辑，熟悉了设计思路后编码还是比较快的。 + +完整代码在http://home.ustc.edu.cn/~guyimin/Legacy/lab3.tar.gz + +sha1:3665575e3f846fdbfa027464c854a3cfbecd393c \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/fsm.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/fsm.png" new file mode 100644 index 0000000..51651db Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/fsm.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/instr_rom.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/instr_rom.coe" new file mode 100644 index 0000000..8a9587b --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/instr_rom.coe" @@ -0,0 +1,34 @@ +memory_initialization_radix=2; +memory_initialization_vector= + 10001100000000010000000000101100, + 00100000000000100000000000000101, + 00100000010000110000000000001001, + 00000000001000100010000000100000, + 10101100000001000000000000110000, + 10001100000001010000000000110000, + 00010000011001000000000000000001, + 00010000001000010000000000000001, + 00001000000000000000000000001000, + 00001000000000000000000000001001, + 0, + 1001, + 0; +; 0 lw $1, $0(0x0) +; 4 lw $2, $0(0x1) + +; 0 addi $1, $0, 8 + +; 0 lw $1, $0(44) +; 4 addi $2, $0, 5 +; 8 addi $3, $2, 9 +; 12 add $4, $1, $2 +; 16 sw $4, $0(48) +; 20 lw $5, $0(48) +; 24 beq $3, $4, +1 +; 28 beq $1, $1, +1 +; 32 j 32 +; 36 j 36 +; memory 8:0 000000000 100000000 + +;00100000000000010000000000001000, +;10001100000000100000000000000001, diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/cpu-multi-cycle-simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/cpu-multi-cycle-simu.v" new file mode 100644 index 0000000..067d6e6 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/cpu-multi-cycle-simu.v" @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +// multiple cycle CPU simu +// 2020 COD Lab4 +// ustcpetergu + +module cpu_multi_cycle_simu(); + reg clk; + reg rst; + + cpu_multi_cycle cpu_multi_cycle_inst + ( + .clk(clk), + .rst(rst), + .m_rf_addr(9'b0) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + initial begin + rst = 1; + + #10 + rst = 0; + + #400 + //rst = 1; + //#10 + //rst = 0; + + #400 + $finish; + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/debug-unit-simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/debug-unit-simu.v" new file mode 100644 index 0000000..e8b2a24 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/debug-unit-simu.v" @@ -0,0 +1,98 @@ +`timescale 1ns / 1ps +// multiple cycle CPU -- DBU simu +// 2020 COD Lab4 +// ustcpetergu + +module debug_unit_multicyc_simu(); + reg clk, rst; + + reg succ; + reg step; + reg [2:0]sel; + reg m_rf; + reg inc; + reg dec; + wire [15:0]led; + wire an; + wire seg; + wire [31:0]seg_data; + debug_unit_multicyc debug_unit_multicyc_inst + ( + .clk(clk), + .rst(rst), + .succ(succ), + .step(step), + .sel(sel), + .m_rf(m_rf), + .inc(inc), + .dec(dec), + + .led(led), + .an(an), + .seg(seg), + + .seg_data(seg_data) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + rst = 1; + succ = 0; + step = 0; + sel = 1; + m_rf = 0; + inc = 0; + dec = 0; + + #10 + rst = 0; + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + + #50 + sel = 2; + #10 + sel = 3; + #10 + sel = 4; + #10 + sel = 5; + #10 + sel = 6; + #10 + sel = 7; + + #10 + sel = 0; + inc = 1; + #10 + inc = 0; + #10 + inc = 1; + #10 + inc = 0; + + #30 + m_rf = 1; + dec = 1; + #10 + dec = 0; + #10 + dec = 1; + #10 + dec = 0; + + #40 + $finish; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" new file mode 100644 index 0000000..f20ca8b --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" @@ -0,0 +1,39 @@ + + + xilinx.com + xci + unknown + 1.0 + + + alu_0 + + + 32 + alu_0 + 32 + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" new file mode 100644 index 0000000..0ce36e2 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" @@ -0,0 +1,44 @@ + + + xilinx.com + xci + unknown + 1.0 + + + edgefetcher_0 + + + + + 100000000 + 0 + 0.000 + 0 + ACTIVE_LOW + edgefetcher_0 + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/ram_0/ram_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/ram_0/ram_0.xci" new file mode 100644 index 0000000..a961944 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/ram_0/ram_0.xci" @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ram_0 + + + 9 + 11111111 + 512 + ./ + zynq + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + ram_0.mif + 2 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 32 + ram_0 + 0 + ce_overrides_sync_controls + ../../../../../test.coe + false + false + 32 + ff + 16 + 512 + non_registered + false + false + non_registered + dual_port_ram + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/cpu-multi-cycle.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/cpu-multi-cycle.v" new file mode 100644 index 0000000..de400b7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/cpu-multi-cycle.v" @@ -0,0 +1,223 @@ +`timescale 1ns / 1ps +// multiple cycle CPU +// 2020 COD Lab4 +// ustcpetergu + +module cpu_multi_cycle + ( + input clk, + input rst, + + output reg [31:0]instruction = 32'hffffffff, + output reg [31:0]pc = 32'hffffffff, + + output reg [31:0]mdr = 32'hffffffff, + + output reg [31:0]ALUOut = 32'hffffffff, + output reg [31:0]A = 32'hffffffff, + output reg [31:0]B = 32'hffffffff, + + output reg PCWriteCond, + output reg PCWrite, + output reg IorD, + output reg MemRead, + output reg MemWrite, + output reg MemtoReg, + output reg IRWrite, + output reg [1:0]PCSource, + output reg [2:0]ALUm, + output reg ALUSrcA, + output reg [1:0]ALUSrcB, + output reg RegWrite, + output reg RegDst, + + output wire ALUZero, + + output wire PCwe, + + input [8:0]m_rf_addr, + output wire [31:0]rf_data, + output wire [31:0]m_data, + + // debug + output wire [31:0]ReadData1, + output wire [31:0]ReadData2, + output reg [31:0]newpc, + output reg [3:0]phase = IF, + + output reg dummy + ); + + wire [31:0]imm = {{16{instruction[15]}}, instruction[15:0]}; + assign PCwe = (ALUZero & PCWriteCond) | PCWrite; + + //reg [31:0]newpc; + + reg [4:0]WriteRegister; + reg [31:0]WriteData; + //wire [31:0]ReadData1; + //wire [31:0]ReadData2; + register_file register_file_inst + ( + .clk(clk), + .ra0(instruction[25:21]), + .ra1(instruction[20:16]), + .ra2(m_rf_addr), + .wa(WriteRegister), + .we(RegWrite), + .wd(WriteData), + .rd0(ReadData1), + .rd1(ReadData2), + .rd2(rf_data) + ); + + reg [31:0]mem_addr; + wire [31:0]MemData; + ram_0 ram_inst + ( + .clk(clk), + .we(MemWrite), + .a(mem_addr[10:2]), + .d(B), + .dpra(m_rf_addr), + .spo(MemData), + .dpo(m_data) + ); + + reg [31:0]ALUIn1; + reg [31:0]ALUIn2; + wire [31:0]ALUResult; + alu_0 alu_0_inst + ( + .m(ALUm), + .a(ALUIn1), + .b(ALUIn2), + .y(ALUResult), + .zf(ALUZero) + //.cf(), + //.of() + ); + + // control unit FSM + // input: instruction[31:26], output: control signals + wire [5:0]Op = instruction[31:26]; + localparam IF = 0; + localparam ID_RF = 1; + localparam MEM_ADDR_CALC = 2; + localparam MEM_ACCESS_LW = 3; + localparam WB = 4; + localparam MEM_ACCESS_SW = 5; + localparam R_EX = 6; + localparam R_END = 7; + localparam BEQ_END = 8; + localparam J_END = 9; + localparam ADDI_END = 10; + localparam BAD = 11; + localparam OP_ADD = 6'b000000; + localparam OP_ADDI = 6'b001000; + localparam OP_LW = 6'b100011; + localparam OP_SW = 6'b101011; + localparam OP_BEQ = 6'b000100; + localparam OP_J = 6'b000010; + //reg [3:0]phase = IF; + always @ (*) begin + PCWriteCond = 0; + PCWrite = 0; + IorD = 0; + MemRead = 0; + MemWrite = 0; + MemtoReg = 0; + IRWrite = 0; + PCSource = 2'b00; + ALUm = 3'b000; + ALUSrcA = 0; + ALUSrcB = 0; + RegWrite = 0; + RegDst = 0; + case (phase) + IF: begin MemRead = 1; ALUSrcB = 2'b01; IRWrite = 1; PCWrite = 1; end + ID_RF: ALUSrcB = 2'b11; + MEM_ADDR_CALC: begin ALUSrcA = 1; ALUSrcB = 2'b10; end + MEM_ACCESS_LW: begin MemRead = 1; IorD = 1; end + ADDI_END: begin RegWrite = 1; end + WB: begin RegWrite = 1; MemtoReg = 1; end + MEM_ACCESS_SW: begin IorD = 1; MemWrite = 1; end + R_EX: ALUSrcA = 1; + R_END: begin RegDst = 1; RegWrite = 1; end + BEQ_END: begin ALUSrcA = 1; ALUm = 3'b001; PCWriteCond = 1; PCSource = 2'b01; end + J_END: begin PCWrite = 1; PCSource = 2'b10; end + default: ; + endcase + end + always @ (posedge clk or posedge rst) begin + if (rst) begin + phase <= IF; + end + else begin + case(phase) + IF: phase <= ID_RF; + ID_RF: + case(Op) + OP_LW: phase <= MEM_ADDR_CALC; + OP_SW: phase <= MEM_ADDR_CALC; + OP_ADDI: phase <= MEM_ADDR_CALC; + OP_ADD: phase <= R_EX; + OP_BEQ: phase <= BEQ_END; + OP_J: phase <= J_END; + default: phase <= BAD; + endcase + MEM_ADDR_CALC: + case (Op) + OP_LW: phase <= MEM_ACCESS_LW; + OP_SW: phase <= MEM_ACCESS_SW; + OP_ADDI: phase <= ADDI_END; + default: phase <= BAD; + endcase + MEM_ACCESS_LW: phase <= WB; + WB: phase <= IF; + MEM_ACCESS_SW: phase <= IF; + ADDI_END: phase <= IF; + R_EX: phase <= R_END; + R_END: phase <= IF; + BEQ_END: phase <= IF; + J_END: phase <= IF; + default: phase <= BAD; + endcase + end + end + + always @ (*) begin + if (IorD) mem_addr = ALUOut; else mem_addr = pc; + if (ALUSrcA) ALUIn1 = A; else ALUIn1 = pc; + if (RegDst) WriteRegister = instruction[15:11]; + else WriteRegister = instruction[20:16]; + if (MemtoReg) WriteData = mdr; + else WriteData = ALUOut; + case (ALUSrcB) + 0: ALUIn2 = B; + 1: ALUIn2 = 4; + 2: ALUIn2 = imm; + 3: ALUIn2 = imm << 2; + endcase + case (PCSource) + 0: newpc = ALUResult; + 1: newpc = ALUOut; + 2: newpc = {pc[31:28], instruction[25:0], 2'b0}; + default: newpc = 32'hffffffff; + endcase + end + always @ (posedge clk) begin + if (rst) begin + pc <= 32'b0; + end + else begin + A <= ReadData1; + B <= ReadData2; + ALUOut <= ALUResult; + mdr <= MemData; + if (PCwe) pc <= newpc; + if (IRWrite) instruction <= MemData; + end + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/debug-unit-multicyc.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/debug-unit-multicyc.v" new file mode 100644 index 0000000..60cfe46 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/debug-unit-multicyc.v" @@ -0,0 +1,155 @@ +`timescale 1ns / 1ps +// multiple cycle CPU -- DBU +// 2020 COD Lab4 +// ustcpetergu + +module debug_unit_multicyc + ( + input clk, + input rst, + input succ, + input step, + input [2:0]sel, + input m_rf, + input inc, + input dec, + + output reg [15:0]led = 0, + output wire [7:0]an, + output wire [6:0]seg, + + output reg [31:0]seg_data = 0 + ); + + seven_segment seven_segment_inst + ( + .clk(clk), + .rst(rst), + .x(seg_data), + .an(an), + .seg(seg) + ); + + wire step_real; + reg step_real_old; + wire inc_real; + wire dec_real; + + edgefetcher_0 edgefetcher_inst_0 + ( + .clk(clk), + .rst(rst), + .y(step), + .p(step_real) + ); + edgefetcher_0 edgefetcher_inst_1 + ( + .clk(clk), + .rst(rst), + .y(inc), + .p(inc_real) + ); + edgefetcher_0 edgefetcher_inst_2 + ( + .clk(clk), + .rst(rst), + .y(dec), + .p(dec_real) + ); + + reg dclk = 0; + reg [8:0]m_rf_addr = 0; + wire [31:0]m_data; + wire [31:0]rf_data; + + wire [1:0]PCSource; + wire PCwe; + wire IorD; + wire MemWrite; + wire IRWrite; + wire RegDst; + wire MemtoReg; + wire RegWrite; + wire [2:0]ALUm; + wire ALUSrcA; + wire [1:0]ALUSrcB; + wire ALUZero; + + wire [31:0]pc; + //wire [31:0]newpc; + wire [31:0]instruction; + wire [31:0]mdr; + wire [31:0]A; + wire [31:0]B; + wire [31:0]ALUOut; + + cpu_multi_cycle cpu_multi_cycle_inst + ( + .clk(dclk), + .rst(rst), + + .instruction(instruction), + .pc(pc), + .mdr(mdr), + .ALUOut(ALUOut), + .A(A), + .B(B), + + .PCSource(PCSource), + .PCwe(PCwe), + .IorD(IorD), + .MemWrite(MemWrite), + .IRWrite(IRWrite), + .RegDst(RegDst), + .MemtoReg(MemtoReg), + .RegWrite(RegWrite), + .ALUm(ALUm), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .ALUZero(ALUZero), + + .m_rf_addr(m_rf_addr), + .rf_data(rf_data), + .m_data(m_data) + ); + + always @ (posedge clk) begin + if (rst) begin + m_rf_addr <= 0; + dclk <= 0; + led <= 16'b0; + step_real_old <= 0; + end + else begin + if (succ == 1) begin dclk <= !dclk; end + else begin + if (step_real) dclk <= !dclk; + else if (step_real_old) dclk <= !dclk; + end + + step_real_old <= step_real; + + if (inc_real) m_rf_addr <= m_rf_addr + 1; + else if (dec_real) m_rf_addr <= m_rf_addr - 1; + + if (sel == 3'b0) + led <= {7'b0, m_rf_addr}; + else + led <= {PCSource, PCwe, IorD, MemWrite, IRWrite, RegDst, MemtoReg, RegWrite, ALUm, ALUSrcA, ALUSrcB, ALUZero}; + case (sel) + 0: begin + if (m_rf == 1) seg_data <= m_data; else seg_data <= rf_data; + end + 1: seg_data <= pc; + 2: seg_data <= instruction; + 3: seg_data <= mdr; + 4: seg_data <= A; + 5: seg_data <= B; + 6: seg_data <= ALUOut; + default: seg_data <= 32'b0; + endcase + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/register_file.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/register_file.v" new file mode 100644 index 0000000..2d34900 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/register_file.v" @@ -0,0 +1,42 @@ +`timescale 1ns / 1ps +// regfile with debug port +// 2020 COD Lab3 +// ustcpetergu + +module register_file + #(parameter WIDTH = 32) + ( + input clk, + input [4:0]ra0, + input [4:0]ra1, + input [4:0]ra2, + input [4:0]wa, + input we, + input [WIDTH-1:0]wd, + output reg [WIDTH-1:0]rd0, + output reg [WIDTH-1:0]rd1, + output reg [WIDTH-1:0]rd2 + ); + + reg [WIDTH-1:0]regfile[31:0]; + initial $readmemh("/home/petergu/MyHome/COD/lab4/regfile.dat", regfile); + + always @ (*) begin + if (ra0 == 5'b0) rd0 = 0; + else rd0 = regfile[ra0]; + if (ra1 == 5'b0) rd1 = 0; + else rd1 = regfile[ra1]; + if (ra2 == 5'b0) rd2 = 0; + else rd2 = regfile[ra2]; + end + + always @ (posedge clk) begin + if (we) begin + if (wa != 5'b0) begin + regfile[wa] <= wd; + end + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/seven-segment.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/seven-segment.v" new file mode 100644 index 0000000..5ff5af9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/seven-segment.v" @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps +// 7-segment digital control +// 2020 COD Lab +// ustcpetergu + +module seven_segment + ( + input clk, + input rst, + input [31:0]x, + output reg [7:0]an, + output reg [6:0]seg + ); + reg [31:0]count = 0; + localparam UPDATE_COUNT = 100000; + reg [2:0]select = 0; + reg [3:0]x0; + always @ (*) begin + case (select) + 0: begin x0 = x[3:0]; an = 8'b11111110; end + 1: begin x0 = x[7:4]; an = 8'b11111101; end + 2: begin x0 = x[11:8]; an = 8'b11111011; end + 3: begin x0 = x[15:12]; an = 8'b11110111; end + 4: begin x0 = x[19:16]; an = 8'b11101111; end + 5: begin x0 = x[23:20]; an = 8'b11011111; end + 6: begin x0 = x[27:24]; an = 8'b10111111; end + 7: begin x0 = x[31:28]; an = 8'b01111111; end + default: begin x0 = 0; an = 0; end + endcase + case (x0) + // +7+ + // 2 6 + // +1+ + // 3 5 + // +4+ + 0: seg = 7'b1000000; + 1: seg = 7'b1111001; + 2: seg = 7'b0100100; + 3: seg = 7'b0110000; + 4: seg = 7'b0011001; + 5: seg = 7'b0010010; + 6: seg = 7'b0000010; + 7: seg = 7'b1111000; + 8: seg = 7'b0000000; + 9: seg = 7'b0010000; + 10: seg = 7'b0001000; + 11: seg = 7'b0000011; + 12: seg = 7'b1000110; + 13: seg = 7'b0100001; + 14: seg = 7'b0000110; + 15: seg = 7'b0001110; + default: seg = 0; + endcase + end + always @ (posedge clk) begin + if (rst) + count <= 0; + else if (count >= UPDATE_COUNT) begin + count <= 0; + select <= select + 1; + end else + count <= count + 1; + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4.tcl" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4.tcl" new file mode 100644 index 0000000..9135019 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/lab4.tcl" @@ -0,0 +1,598 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1 (64-bit) +# +# lab4.tcl: Tcl script for re-creating project 'lab4-cpu-multi-cycle' +# +# Generated by Vivado on Fri Jun 05 10:37:14 CST 2020 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (lab4.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/cpu-multi-cycle.v" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/register_file.v" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/seven-segment.v" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/debug-unit-multicyc.v" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/ram_0/ram_0.xci" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/cpu-multi-cycle-simu.v" +# "/home/petergu/MyHome/COD/lab4/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/debug-unit-simu.v" +# +# 3. The following remote source files that were added to the original project:- +# +# "/home/petergu/MyHome/COD/lab4/test.coe" +# "/home/petergu/MyHome/COD/lab4/instr_rom.coe" +# "/home/petergu/MyHome/COD/ip/regfile/component.xml" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "lab4-cpu-multi-cycle" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "lab4.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/lab4-cpu-multi-cycle"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "www.digilentinc.com:pynq-z1:part0:1.0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "pynq-z1" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "11" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "11" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "11" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "11" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "11" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "11" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "11" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "32" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/test.coe"] \ + [file normalize "${origin_dir}/instr_rom.coe"] \ + [file normalize "${origin_dir}/../ip/regfile/component.xml"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/cpu-multi-cycle.v" ]\ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/register_file.v" ]\ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/seven-segment.v" ]\ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/new/debug-unit-multicyc.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../ip/regfile/component.xml" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "IP-XACT" -objects $file_obj + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "debug_unit_multicyc" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/alu_0/alu_0.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "alu_0/alu_0.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/edgefetcher_0/edgefetcher_0.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "edgefetcher_0/edgefetcher_0.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sources_1/ip/ram_0/ram_0.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "ram_0/ram_0.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/cpu-multi-cycle-simu.v" ]\ + [file normalize "${origin_dir}/lab4-cpu-multi-cycle/lab4-cpu-multi-cycle.srcs/sim_1/new/debug-unit-simu.v" ]\ +] +set imported_files [import_files -fileset sim_1 $files] + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "cpu_multi_cycle_simu" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "xsim.simulate.log_all_signals" -value "1" -objects $obj +set_property -name "xsim.simulate.saif_all_signals" -value "1" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/logic.png" 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"b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic2.png" new file mode 100644 index 0000000..f129d7c Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic2.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic3.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic3.png" new file mode 100644 index 0000000..0b7762a Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic3.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic4.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic4.png" new file mode 100644 index 0000000..df74dc4 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/pic4.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/regfile.dat" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/regfile.dat" new file mode 100644 index 0000000..987bac9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/regfile.dat" @@ -0,0 +1,32 @@ +0000f000 +0000f001 +0000f002 +0000f003 +0000f004 +0000f005 +0000f006 +0000f007 +0000f008 +0000f009 +0000f00a +0000f00b +0000f00c +0000f00d +0000f00e +0000f00f +0000f010 +0000f011 +0000f012 +0000f013 +0000f014 +0000f015 +0000f016 +0000f017 +0000f018 +0000f019 +0000f01a +0000f01b +0000f01c +0000f01d +0000f01e +0000f01f diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/report.md" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/report.md" new file mode 100644 index 0000000..a57163c --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/report.md" @@ -0,0 +1,228 @@ +## Lab4 多周期CPU + +古宜民 PB17000002 + +2020.6.5 + +### CPU + +数据通路和状态设计 + +数据通路为文档上的逻辑图： + +![](logic.png) + +其中指令寄存器处，接入地址为`pc[10:2]`。 + +时序部分，每个周期需要更新寄存器A，B，MDR，ALUOut，以及PC和Instruction的值。 + +```verilog + always @ (posedge clk) begin + if (rst) begin + pc <= 32'b0; + end + else begin + A <= ReadData1; + B <= ReadData2; + ALUOut <= ALUResult; + mdr <= MemData; + if (PCwe) pc <= newpc; + if (IRWrite) instruction <= MemData; + end + end +endmodule +``` + +数据通路由控制信号通过组合逻辑控制： + +```verilog + always @ (*) begin + if (IorD) mem_addr = ALUOut; else mem_addr = pc; + if (ALUSrcA) ALUIn1 = A; else ALUIn1 = pc; + if (RegDst) WriteRegister = instruction[15:11]; + else WriteRegister = instruction[20:16]; + if (MemtoReg) WriteData = mdr; + else WriteData = ALUOut; + case (ALUSrcB) + 0: ALUIn2 = B; + 1: ALUIn2 = 4; + 2: ALUIn2 = imm; + 3: ALUIn2 = imm << 2; + endcase + case (PCSource) + 0: newpc = ALUResult; + 1: newpc = ALUOut; + 2: newpc = {pc[31:28], instruction[25:0], 2'b0}; + default: newpc = 32'hffffffff; + endcase + end +``` + +控制信号由Control状态机生成，如PPT中给出的状态机： + +为了实现ADDI指令，需要加入一个状态Addi completion，并增加Memory address computation->Addi completion->Instruction fetch的跳转。 + +![](fsm.png) + +```verilog + // control unit FSM + // input: instruction[31:26], output: control signals + wire [5:0]Op = instruction[31:26]; + localparam IF = 0; + localparam ID_RF = 1; + localparam MEM_ADDR_CALC = 2; + localparam MEM_ACCESS_LW = 3; + localparam WB = 4; + localparam MEM_ACCESS_SW = 5; + localparam R_EX = 6; + localparam R_END = 7; + localparam BEQ_END = 8; + localparam J_END = 9; + localparam ADDI_END = 10; + localparam BAD = 11; + localparam OP_ADD = 6'b000000; + localparam OP_ADDI = 6'b001000; + localparam OP_LW = 6'b100011; + localparam OP_SW = 6'b101011; + localparam OP_BEQ = 6'b000100; + localparam OP_J = 6'b000010; + //reg [3:0]phase = IF; + always @ (*) begin + PCWriteCond = 0; + PCWrite = 0; + IorD = 0; + MemRead = 0; + MemWrite = 0; + MemtoReg = 0; + IRWrite = 0; + PCSource = 2'b00; + ALUm = 3'b000; + ALUSrcA = 0; + ALUSrcB = 0; + RegWrite = 0; + RegDst = 0; + case (phase) + IF: begin MemRead = 1; ALUSrcB = 2'b01; IRWrite = 1; PCWrite = 1; end + ID_RF: ALUSrcB = 2'b11; + MEM_ADDR_CALC: begin ALUSrcA = 1; ALUSrcB = 2'b10; end + MEM_ACCESS_LW: begin MemRead = 1; IorD = 1; end + ADDI_END: begin RegWrite = 1; end + WB: begin RegWrite = 1; MemtoReg = 1; end + MEM_ACCESS_SW: begin IorD = 1; MemWrite = 1; end + R_EX: ALUSrcA = 1; + R_END: begin RegDst = 1; RegWrite = 1; end + BEQ_END: begin ALUSrcA = 1; ALUm = 3'b001; PCWriteCond = 1; PCSource = 2'b01; end + J_END: begin PCWrite = 1; PCSource = 2'b10; end + default: ; + endcase + end + always @ (posedge clk or posedge rst) begin + if (rst) begin + phase <= IF; + end + else begin + case(phase) + IF: phase <= ID_RF; + ID_RF: + case(Op) + OP_LW: phase <= MEM_ADDR_CALC; + OP_SW: phase <= MEM_ADDR_CALC; + OP_ADDI: phase <= MEM_ADDR_CALC; + OP_ADD: phase <= R_EX; + OP_BEQ: phase <= BEQ_END; + OP_J: phase <= J_END; + default: phase <= BAD; + endcase + MEM_ADDR_CALC: + case (Op) + OP_LW: phase <= MEM_ACCESS_LW; + OP_SW: phase <= MEM_ACCESS_SW; + OP_ADDI: phase <= ADDI_END; + default: phase <= BAD; + endcase + MEM_ACCESS_LW: phase <= WB; + WB: phase <= IF; + MEM_ACCESS_SW: phase <= IF; + ADDI_END: phase <= IF; + R_EX: phase <= R_END; + R_END: phase <= IF; + BEQ_END: phase <= IF; + J_END: phase <= IF; + default: phase <= BAD; + endcase + end + end +``` + +仿真结果： + +使用助教提供的程序： + +![](pic2.png) + +![](pic1.png) + +全部波形如图，可见每一条指令的执行过程。其中标注出了一部分指令的特征信号。 + +![](pic3.png) + +仿真开始的几条指令，从中可见四个addi均正确得出了值（3，5，1，0）并RegWrite写回了目标寄存器。 + +### DBU + +本实验的DBU通过控制发送给CPU的时钟信号实现调试。其他内容与lab3的DBU几乎相同。 + +仿真结果： +![](pic4.png) + +图为CPU运行2个周期后查看各个信号的值，演示了读取信号和寄存器、内存地址的功能。 + +主要代码： + +```verilog + always @ (posedge clk) begin + if (rst) begin + m_rf_addr <= 0; + dclk <= 0; + led <= 16'b0; + step_real_old <= 0; + end + else begin + if (succ == 1) begin dclk <= !dclk; end + else begin + if (step_real) dclk <= !dclk; + else if (step_real_old) dclk <= !dclk; + end + + step_real_old <= step_real; + + if (inc_real) m_rf_addr <= m_rf_addr + 1; + else if (dec_real) m_rf_addr <= m_rf_addr - 1; + + if (sel == 3'b0) + led <= {7'b0, m_rf_addr}; + else + led <= {PCSource, PCwe, IorD, MemWrite, IRWrite, RegDst, MemtoReg, RegWrite, ALUm, ALUSrcA, ALUSrcB, ALUZero}; + case (sel) + 0: begin + if (m_rf == 1) seg_data <= m_data; else seg_data <= rf_data; + end + 1: seg_data <= pc; + 2: seg_data <= instruction; + 3: seg_data <= mdr; + 4: seg_data <= A; + 5: seg_data <= B; + 6: seg_data <= ALUOut; + default: seg_data <= 32'b0; + endcase + end + end +``` + +### 总结 + +多周期CPU相比单周期稍微复杂了一些，因为仿真时间较长并且信号较多略有“混乱”，比如寄存器堆和内存读结果等在一些周期未被使用，但是仍有变化的输出，这增加了调试的难度。 + +完整代码在http://home.ustc.edu.cn/~guyimin/Legacy/lab4.tar.gz + +sha1:f44bedc8196e0709ce59bfe68047f2e395d46f08 \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/sim.asm" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/sim.asm" new file mode 100644 index 0000000..a2dcc7f --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/sim.asm" @@ -0,0 +1,46 @@ +# 本文档存储器以字编址 +# 本文档存储器以字编址 +# 本文档存储器以字编址 +# 初始PC = 0x00000000 + + j _start # 0 + +.data + .word 0,6,0,8,0x80000000,0x80000100,0x100,5,0,0,0 #编译成机器码时，编译器会在前面多加个0，所以后面lw指令地址会多加4 + +_start: + addi $t0,$0,3 #t0=3 44 + addi $t1,$0,5 #t1=5 48 + addi $t2,$0,1 #t2=1 52 + addi $t3,$0,0 #t3=0 56 + + add $s0,$t1,$t0 #s0=t1+t0=8 测试add指令 60 + lw $s1,12($0) # 64 + beq $s1,$s0,_next1 #正确跳到_next 68 + + j _fail + +_next1: + lw $t0, 16($0) #t0 = 0x80000000 76 + lw $t1, 20($0) #t1 = 0x80000100 80 + + add $s0,$t1,$t0 #s0 = 0x00000100 = 256 84 + lw $s1, 24($0) # 88 + beq $s1,$s0,_next2 #正确跳到_success 92 + + j _fail + +_next2: + add $0, $0, $t2 #$0应该一直为0 100 + beq $0,$t3,_success # 104 + + +_fail: + sw $t3,8($0) #失败通过看存储器地址0x08里值，若为0则测试不通过，最初地址0x08里值为0 108 + j _fail + +_success: + sw $t2,8($0) #全部测试通过，存储器地址0x08里值为1 116 + j _success + + #判断测试通过的条件是最后存储器地址0x08里值为1，说明全部通过测试 \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/test.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/test.coe" new file mode 100644 index 0000000..d2a0fc9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab4/test.coe" @@ -0,0 +1,67 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +0800000b +00000006 +00000000 +00000008 +80000000 +80000100 +00000100 +00000005 +00000000 +00000000 +00000000 +20080003 +20090005 +200a0001 +200b0000 +01288020 +8c11000c +12300001 +0800001b +8c080010 +8c090014 +01288020 +8c110018 +12300001 +0800001b +000a0020 +100b0002 +ac0b0008 +0800001b +ac0a0008 +0800001d + +; j 11 +; 6 +; 0 +; 8 +; 0x80000000 +; 0x80000100 +; 0x100 +; 5 +; 0 +; 0 +; 0 +; addi $8, $0, 3 +; addi $9, $0, 5 +; addi $10, $0, 1 +; addi $11, $0, 0 +; add $16, $9, $8 //8 +; lw $17, 12($0) //8 +; beq $17, $16, +1 //jump +; j 27 +; lw $16, 16($0) //0x80000000 +; lw $17, 20($0) //0x80000100 +; add $16, $9, $8 //0x100 +; lw $17, 24($0) //0x100 +; beq $16, $17, +1 //jump +; j 27 +; add $0, $0, $10 //0 +; beq $0, $11, +2 //jump +; sw $11, 8($0) +; j 27 +; sw $10, 8($0) //here +; j 29 + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/1.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/1.png" new file mode 100644 index 0000000..d0f8d30 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/1.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/2.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/2.png" new file mode 100644 index 0000000..f7f956b Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/2.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/3.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/3.png" new file mode 100644 index 0000000..68ac373 Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/3.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/data_1.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/data_1.coe" new file mode 100644 index 0000000..700e7a0 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/data_1.coe" @@ -0,0 +1,11 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +00000000 +00000006 +00000000 +00000010 +80000000 +80000100 +00000100 +00000005 +00000000 \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/data_2.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/data_2.coe" new file mode 100644 index 0000000..f3171d7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/data_2.coe" @@ -0,0 +1,11 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +00000000 +00000001 +00000002 +00000003 +80000000 +80000100 +00000100 +00000005 +00000000 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/ins_1.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/ins_1.coe" new file mode 100644 index 0000000..bed8c76 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/ins_1.coe" @@ -0,0 +1,29 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +20080003 +21090002 +200a0001 +200b0000 +01288020 +02108020 +8c11000c + +12300001 + +08000011 +8c080010 +8c090014 +01288020 +8c110018 + +12300001 + +08000011 +000a0020 + +100b0002 + +ac0b0008 +08000011 +ac0a0008 +08000013 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/ins_2.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/ins_2.coe" new file mode 100644 index 0000000..ccc2f84 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/ins_2.coe" @@ -0,0 +1,25 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +00004820 +08000002 +200a0001 +214a0001 +014a5020 +214afffc +11400001 +08000015 +21290001 +0800000a +20000004 +8c0a0004 +8c0b0008 +014b6020 +ac0c0000 +8c0d0000 +8c0e000c +11ae0001 +08000015 +21290001 +08000016 +08000015 +08000016 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/cpu_pipeline_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/cpu_pipeline_simu.v" new file mode 100644 index 0000000..7beb4ec --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/cpu_pipeline_simu.v" @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +// pipeline CPU simu +// 2020 COD Lab5 +// ustcpetergu + +module cpu_pipeline_simu(); + reg clk; + reg rst; + + cpu_pipeline cpu_pipeline_inst + ( + .clk(clk), + .rst(rst), + .m_rf_addr(0) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + initial begin + rst = 1; + #10 + rst = 0; + #1000 + $finish; + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/pipeline_dbu_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/pipeline_dbu_simu.v" new file mode 100644 index 0000000..fd083f0 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/pipeline_dbu_simu.v" @@ -0,0 +1,142 @@ +`timescale 1ns / 1ps +// pipeline cycle CPU -- DBU simu +// 2020 COD Lab5 +// ustcpetergu + + +module pipeline_dbu_simu(); + reg clk, rst; + + reg succ; + reg step; + reg [2:0]sel; + reg [1:0]sel2; + reg m_rf; + reg inc; + reg dec; + wire [15:0]led; + wire an; + wire seg; + wire [31:0]seg_data; + + pipeline_dbu pipeline_dbu_inst + ( + .clk(clk), + .rst(rst), + .succ(succ), + .step(step), + .sel(sel), + .sel2(sel2), + .m_rf(m_rf), + .inc(inc), + .dec(dec), + + .led(led), + .an(an), + .seg(seg), + + .seg_data(seg_data) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + rst = 1; + #10 + rst = 0; + //#1000 + rst = 1; + succ = 0; + step = 0; + sel = 1; + sel2 = 0; + m_rf = 0; + inc = 0; + dec = 0; + + #40 + rst = 0; + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + #10 + step = 1; + #10 + step = 0; + + #50 + sel = 2; + sel2 = 0; + #10 + sel2 = 1; + #10 + sel2 = 2; + #10 + sel2 = 3; + #10 + sel2 = 0; + sel = 3; + #10 + sel = 4; + #10 + sel = 5; + + #10 + sel = 0; + inc = 1; + #10 + inc = 0; + #10 + inc = 1; + #10 + inc = 0; + + #30 + m_rf = 1; + dec = 1; + #10 + dec = 0; + #10 + dec = 1; + #10 + dec = 0; + + #40 + $finish; + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/alu_0/alu_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/alu_0/alu_0.xci" new file mode 100644 index 0000000..f20ca8b --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/alu_0/alu_0.xci" @@ -0,0 +1,39 @@ + + + xilinx.com + xci + unknown + 1.0 + + + alu_0 + + + 32 + alu_0 + 32 + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 1 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" new file mode 100644 index 0000000..d13dc87 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dist_mem_gen_0 + + + 8 + 10111011 + 256 + ./ + zynq + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + dist_mem_gen_0.mif + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 32 + dist_mem_gen_0 + 0 + ce_overrides_sync_controls + ../../../../../ins_2.coe + false + false + 32 + bb + 16 + 256 + non_registered + false + false + non_registered + rom + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_1/dist_mem_gen_1.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_1/dist_mem_gen_1.xci" new file mode 100644 index 0000000..5cdb2b4 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_1/dist_mem_gen_1.xci" @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + dist_mem_gen_1 + + + 8 + 10111011 + 256 + ./ + zynq + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + dist_mem_gen_1.mif + 2 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 32 + dist_mem_gen_1 + 0 + ce_overrides_sync_controls + ../../../../../data_2.coe + false + false + 32 + bb + 16 + 256 + non_registered + false + false + non_registered + dual_port_ram + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + www.digilentinc.com:pynq-z1:part0:1.0 + + xc7z020 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 13 + TRUE + . + + . + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/cpu-pipeline.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/cpu-pipeline.v" new file mode 100644 index 0000000..e147012 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/cpu-pipeline.v" @@ -0,0 +1,463 @@ +`timescale 1ns / 1ps +// pipeline CPU +// 2020 COD Lab5 +// ustcpetergu + +module cpu_pipeline + ( + input clk, + input rst, + + output reg [31:0]pc = 0, + + output reg [31:0]npc_ifid = 0, + output reg [31:0]ir_ifid = 0, + + output reg [31:0]npc_idex = 0, + output reg [31:0]A_idex = 0, + output reg [31:0]B_idex = 0, + output reg [31:0]imm_idex = 0, + output reg [31:0]ir_idex = 0, + output reg RegWrite_idex = 0, + output reg MemtoReg_idex = 0, + output reg Branch_idex = 0, + output reg MemRead_idex = 0, + output reg MemWrite_idex = 0, + output reg RegDst_idex = 0, + output reg [2:0]ALUOp_idex = 0, + output reg ALUSrc_idex = 0, + output reg Jump_idex = 0, + + output reg [31:0]npc_exmem = 0, + output reg ZF_exmem = 0, + output reg [31:0]Y_exmem = 0, + output reg [31:0]B_exmem = 0, + output reg [31:0]imm_exmem = 0, + output reg [31:0]ir_exmem = 0, + output reg [4:0]WA_exmem = 0, + output reg RegWrite_exmem = 0, + output reg MemtoReg_exmem = 0, + output reg Branch_exmem = 0, + output reg MemRead_exmem = 0, + output reg MemWrite_exmem = 0, + output reg Jump_exmem = 0, + + output reg [31:0]MDR_memwb = 0, + output reg [31:0]Y_memwb = 0, + output reg [4:0]WA_memwb = 0, + output reg [31:0]ir_memwb = 0, + output reg RegWrite_memwb = 0, + output reg MemtoReg_memwb = 0, + + output wire PCSrc, + + input [7:0]m_rf_addr, + output [31:0]rf_data, + output [31:0]m_data, + + output dummy + ); + + wire [31:0]instruction; + dist_mem_gen_0 dist_mem_gen_0_inst + ( + .a(pc[9:2]), + .spo(instruction) + ); + + wire [31:0]ReadData_ram; + dist_mem_gen_1 dist_mem_gen_1_inst + ( + .clk(clk), + .we(MemWrite_exmem), + .a(Y_exmem[9:2]), + .d(B_exmem), + .dpra(m_rf_addr), + .spo(ReadData_ram), + .dpo(m_data) + ); + + reg [31:0]ALUa; + reg [31:0]ALUb; + wire [31:0]ALUy; + wire ALUZero; + alu_0 alu_0_inst + ( + .m(ALUOp_idex), + .a(ALUa), + .b(ALUb), + .y(ALUy), + .zf(ALUZero) + ); + + reg [31:0]WriteData; + wire [31:0]ReadData1; + wire [31:0]ReadData2; + register_file register_file_inst + ( + .clk(clk), + .ra0(ir_ifid[25:21]), + .ra1(ir_ifid[20:16]), + .ra2(m_rf_addr), + .wa(WA_memwb), + .we(RegWrite_memwb), + .wd(WriteData), + .rd0(ReadData1), + .rd1(ReadData2), + .rd2(rf_data) + ); + + // forwarding unit + reg exmem2ALUA; + reg exmem2ALUB; + reg exmem2DataMem; + reg memwb2ALUA; + reg memwb2ALUB; + reg memwb2DataMem; + always @ (*) begin + exmem2ALUA = 0; + exmem2ALUB = 0; + exmem2DataMem = 0; + memwb2ALUA = 0; + memwb2ALUB = 0; + memwb2DataMem = 0; + + // ADDI + LW + // ADDI + SW(ex) + // ADDI + ADDI + // ADDI + R(A) + // ADDI + BEQ(A) + // exmem(ALUOut) to ALUIn A + // ADDI + R(B) + // ADDI + BEQ(B) + // exmem(ALUOut) to ALUIn B + if ((ir_exmem[31:26] == 6'b001000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[20:16] != 5'b0 & ir_exmem[20:16] == ir_idex[25:21]) exmem2ALUA = 1; + if ((ir_exmem[31:26] == 6'b001000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[20:16] != 5'b0 & ir_exmem[20:16] == ir_idex[20:16]) exmem2ALUB = 1; + + // R + LW + // R + SW(ex) + // R + ADDI + // R + R(A) + // R + BEQ(A) + // exmem(ALUOut) to ALUIn A + // R + R(B) + // R + BEQ(B) + // exmem(ALUOut) to ALUIn B + if ((ir_exmem[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[15:11] != 5'b0 & ir_exmem[15:11] == ir_idex[25:21]) exmem2ALUA = 1; + if ((ir_exmem[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[15:11] != 5'b0 & ir_exmem[15:11] == ir_idex[20:16]) exmem2ALUB = 1; + + // LW + * + LW + // LW + * + SW(wb) + // LW + * + ADDI + // LW + * + R(A) + // LW + * + BEQ(A) + // ADDI + * + LW + // ADDI + * + SW(ex) + // ADDI + * + ADDI + // ADDI + * + R(A) + // ADDI + * + BEQ(A) + // memwb(ALUOut or MDR) to ALUIn A + // LW + * + R(B) + // LW + * + BEQ(B) + // ADDI + * + R(B) + // ADDI + * + BEQ(B) + // memwb(ALUOut or MDR) to ALUIn B + if ((ir_memwb[31:26] == 6'b100011 | ir_memwb[31:26] == 6'b001000 | ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[20:16] != 5'b0 & ir_memwb[20:16] == ir_idex[25:21]) memwb2ALUA = 1; + if ((ir_memwb[31:26] == 6'b100011 | ir_memwb[31:26] == 6'b001000 | ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[20:16] != 5'b0 & ir_memwb[20:16] == ir_idex[20:16]) memwb2ALUB = 1; + // R + * + LW + // R + * + SW(ex) + // R + * + ADDI + // R + * + R(A) + // R + * + BEQ(A) + // memwb(ALUOut) to ALUIn A + // R + * + R(B) + // R + * + BEQ(B) + // memwb(ALUOut) to ALUIn B + if ((ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[15:11] != 5'b0 & ir_memwb[15:11] == ir_idex[25:21]) memwb2ALUA = 1; + if ((ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[15:11] != 5'b0 & ir_memwb[15:11] == ir_idex[20:16]) memwb2ALUB = 1; + + // R + SW(wb) + // exmem(ALUOut) to DataMemory(B_exmem) + // R + * + SW(wb) + // memwb(ALUOut) to DataMemory(B_exmem) + // LW + SW(wb) + // memwb(MDR) to DataMemory(B_exmem) + if ((ir_exmem[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b101011) & + ir_exmem[15:11] != 5'b0 & ir_exmem[15:11] == ir_idex[20:16]) exmem2DataMem = 1; + if ((ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b101011) & + ir_memwb[15:11] != 5'b0 & ir_memwb[15:11] == ir_idex[20:16]) memwb2DataMem = 1; + if ((ir_memwb[31:26] == 6'b100011) & + (ir_idex[31:26] == 6'b101011) & + ir_memwb[20:16] != 5'b0 & ir_memwb[20:16] == ir_idex[20:16]) exmem2DataMem = 1; + + end + + // hazard detection unit + reg nPCWrite; + reg nIFIDWrite; + reg nControl; + always @ (*) begin + // LW + R(A, B) + // LW + LW + // LW + ADDI + // LW + SW(ex) + // LW + BEQ(A, B) + // stall + if (ir_idex[31:26] == 6'b100011 & ( + (ir_idex[20:16] != 5'b0 & ir_idex[20:16] == ir_ifid[25:21] & (ir_ifid[31:26] == 6'b000000 | ir_ifid[31:26] == 6'b100011 | ir_ifid[31:26] == 6'b001000 | ir_ifid[31:26] == 6'b101011 | ir_ifid[31:26] == 6'b000100)) | + (ir_idex[20:16] != 5'b0 & ir_idex[20:16] == ir_ifid[20:16] & (ir_ifid[31:26] == 6'b000000 | ir_ifid[31:26] == 6'b000100)) + )) begin + nPCWrite = 1; + nIFIDWrite = 1; + nControl = 1; + end + else begin + nPCWrite = 0; + nIFIDWrite = 0; + nControl = 0; + end + end + + // control unit + assign PCSrc = ZF_exmem & Branch_exmem; + assign Flush = Jump_exmem | PCSrc; + reg RegWrite; + reg MemtoReg; + reg Branch; + reg MemRead; + reg MemWrite; + reg RegDst; + reg ALUOp; + reg ALUSrc; + reg Jump; + always @ (*) begin + RegWrite = 0; + MemtoReg = 0; + Branch = 0; + MemRead = 0; + MemWrite = 0; + RegDst = 0; + ALUOp = 3'b0; + ALUSrc = 0; + Jump = 0; + case (ir_ifid[31:26]) + 6'b000000: + case (ir_ifid[5:0]) + // add--- --rs- --rt- --rd- shamt funct- + 6'b100000: begin RegDst = 1; RegWrite = 1; end + default: ; + endcase + // addi-- --rs- --rt- ----immediate--- + 6'b001000: begin ALUSrc = 1; RegWrite = 1; end + // lw---- --rs- --rt- ----addr-------- + 6'b100011: begin ALUSrc = 1; RegWrite = 1; MemRead = 1; MemtoReg = 1; end + // sw---- --rs- --rt- ----addr-------- + 6'b101011: begin ALUSrc = 1; MemWrite = 1; end + // beq-- --rs- --rt- ----addr-------- + 6'b000100: begin Branch = 1; ALUOp = 3'b001; end + // j---- ----addr------------------ + 6'b000010: begin Jump = 1; end + default: ; + endcase + end + always @ (posedge clk) begin + if (rst) begin + RegWrite_idex <= 0; + MemtoReg_idex <= 0; + Branch_idex <= 0; + MemRead_idex <= 0; + MemWrite_idex <= 0; + RegDst_idex <= 0; + ALUOp_idex <= 0; + ALUSrc_idex <= 0; + Jump_idex <= 0; + + RegWrite_exmem <= 0; + MemtoReg_exmem <= 0; + Branch_exmem <= 0; + MemRead_exmem <= 0; + MemWrite_exmem <= 0; + Jump_exmem <= 0; + + RegWrite_memwb <= 0; + MemtoReg_memwb <= 0; + end + else begin + // control -- idex + if (nControl == 0 & Flush== 0) begin + RegWrite_idex <= RegWrite; + MemtoReg_idex <= MemtoReg; + Branch_idex <= Branch; + MemRead_idex <= MemRead; + MemWrite_idex <= MemWrite; + RegDst_idex <= RegDst; + ALUOp_idex <= ALUOp; + ALUSrc_idex <= ALUSrc; + Jump_idex <= Jump; + end + else begin + RegWrite_idex <= 0; + MemtoReg_idex <= 0; + Branch_idex <= 0; + MemRead_idex <= 0; + MemWrite_idex <= 0; + RegDst_idex <= 0; + ALUOp_idex <= 3'b0; + ALUSrc_idex <= 0; + Jump_idex <= 0; + end + + // control -- exmem + // this flush is actually unnecessary + if (Flush) begin + RegWrite_exmem <= 0; + MemtoReg_exmem <= 0; + Branch_exmem <= 0; + MemRead_exmem <= 0; + MemWrite_exmem <= 0; + Jump_exmem <= 0; + end + else begin + RegWrite_exmem <= RegWrite_idex; + MemtoReg_exmem <= MemtoReg_idex; + Branch_exmem <= Branch_idex; + MemRead_exmem <= MemRead_idex; + MemWrite_exmem <= MemWrite_idex; + Jump_exmem <= Jump_idex; + end + + // control -- memwb + RegWrite_memwb <= RegWrite_exmem; + MemtoReg_memwb <= MemtoReg_exmem; + end + end + + always @ (*) begin + // with forwarding + if (exmem2ALUA) ALUa = Y_exmem; + else if (memwb2ALUA) ALUa = WriteData; + else ALUa = A_idex; + end + always @ (*) begin + // with forwarding + if (exmem2ALUB) ALUb = Y_exmem; + else if (memwb2ALUB) ALUb = WriteData; + else if (ALUSrc_idex) ALUb = imm_idex; + else ALUb = B_idex; + end + always @ (*) begin + if (MemtoReg_memwb) WriteData = MDR_memwb; + else WriteData = Y_memwb; + end + always @ (posedge clk) begin + if (rst) begin + pc <= 0; + + npc_ifid <= 0; + ir_ifid <= 0; + + npc_idex <= 0; + A_idex <= 0; + B_idex <= 0; + imm_idex <= 0; + ir_idex <= 0; + + npc_exmem <= 0; + ZF_exmem <= 0; + Y_exmem <= 0; + B_exmem <= 0; + imm_exmem <= 0; + ir_exmem <= 0; + WA_exmem <= 0; + + MDR_memwb <= 0; + Y_memwb <= 0; + WA_memwb <= 0; + ir_memwb <= 0; + end + else begin + // pc + // with interlock + if (nPCWrite == 0) begin + if (Jump_exmem) pc <= {4'b0000, ir_exmem[25:0], 2'b00}; + else if (PCSrc) pc <= npc_exmem; + else pc <= pc + 4; + end + + // data -- ifid + // with interlock + if (Flush) begin + npc_ifid <= 0; + ir_ifid <= 0; + end + else if (nIFIDWrite == 0) begin + npc_ifid <= pc + 4; + ir_ifid <= instruction; + end + + // data -- idex + if (Flush) begin + npc_idex <= 0; + A_idex <= 0; + B_idex <= 0; + imm_idex <= 0; + ir_ifid <= 0; + end + else begin + npc_idex <= npc_ifid; + A_idex <= ReadData1; + B_idex <= ReadData2; + imm_idex <= {{16{ir_ifid[15]}}, ir_ifid[15:0]}; + ir_idex <= ir_ifid; + end + + // data -- exmem + // this flush is actually unnecessary + if (Flush) begin + npc_exmem <= 0; + ZF_exmem <= 0; + Y_exmem <= 0; + imm_idex <= 0; + WA_exmem <= 0; + B_exmem <= 0; + end + else begin + npc_exmem <= npc_idex + (imm_idex << 2); + ZF_exmem <= ALUZero; + Y_exmem <= ALUy; + imm_exmem <= imm_idex; + if (RegDst_idex) WA_exmem <= ir_idex[15:11]; + else WA_exmem <= ir_idex[20:16]; + ir_exmem <= ir_idex; + // with forwarding + if (exmem2DataMem) B_exmem <= Y_exmem; + else B_exmem <= B_idex; + end + + // data -- memwb + MDR_memwb <= ReadData_ram; + Y_memwb <= Y_exmem; + WA_memwb <= WA_exmem; + ir_memwb <= ir_exmem; + end + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/pipeline_dbu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/pipeline_dbu.v" new file mode 100644 index 0000000..4ab83e5 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/pipeline_dbu.v" @@ -0,0 +1,245 @@ +`timescale 1ns / 1ps +// pipeline cycle CPU -- DBU +// 2020 COD Lab5 +// ustcpetergu + +module edgefetcher + ( + input clk, rst, + input y, + output p + ); + reg [1:0]state = 0; + reg [1:0]next_state = 0; + assign p = (state == 1); + always @ (posedge clk) begin + if (rst) begin + state <= 0; + next_state <= 0; + end + else state <= next_state; + end + always @ (*) begin + next_state = state; + case (state) + 0: if (y) next_state = 1; + 1: if (y) next_state = 2; else next_state = 0; + 2: if (y) next_state = 2; else next_state = 0; + default: next_state = 0; + endcase + end +endmodule + +module pipeline_dbu + ( + input clk, + input rst, + input succ, + input step, + input [2:0]sel, + input [1:0]sel2, + input m_rf, + input inc, + input dec, + + output reg [15:0]led = 0, + output wire [7:0]an, + output wire [6:0]seg, + + output reg [31:0]seg_data = 0 + + ); + + seven_segment seven_segment_inst + ( + .clk(clk), + .rst(rst), + .x(seg_data), + .an(an), + .seg(seg) + ); + + wire step_real; + reg step_real_old = 0; + wire inc_real; + wire dec_real; + + edgefetcher edgefetcher_inst + ( + .clk(clk), + .rst(rst), + .y(step), + .p(step_real) + ); + edgefetcher edgefetcher_inst_1 + ( + .clk(clk), + .rst(rst), + .y(inc), + .p(inc_real) + ); + edgefetcher edgefetcher_inst_2 + ( + .clk(clk), + .rst(rst), + .y(dec), + .p(dec_real) + ); + + reg dclk = 0; + reg [7:0]m_rf_addr = 0; + wire [31:0]m_data; + wire [31:0]rf_data; + + wire [31:0]pc; + + wire [31:0]npc_ifid; + wire [31:0]ir_ifid; + + wire [31:0]npc_idex; + wire [31:0]ir_idex; + wire [31:0]A_idex; + wire [31:0]B_idex; + wire RegWrite_idex; + wire MemtoReg_idex; + wire Branch_idex; + wire MemRead_idex; + wire RegDst_idex; + wire [2:0]ALUOp_idex; + wire ALUSrc_idex; + wire Jump_idex; + + wire [31:0]npc_exmem; + wire [31:0]ir_exmem; + wire [31:0]Y_exmem; + wire [31:0]imm_exmem; + wire RegWrite_exmem; + wire MemtoReg_exmem; + wire Branch_exmem; + wire MemWrite_exmem; + wire MemRead_exmem; + wire MemWrite_idex; + wire Jump_exmem; + + wire [31:0]MDR_memwb; + wire [31:0]ir_memwb; + wire [31:0]Y_memwb; + wire [31:0]WA_memwb; + wire RegWrite_memwb; + wire MemtoReg_memwb; + + cpu_pipeline cpu_pipeline_inst + ( + .clk(dclk), + //.clk(clk), + .rst(rst), + + .pc(pc), + + .npc_ifid(npc_ifid), + .ir_ifid(ir_ifid), + + .npc_idex(npc_idex), + .ir_idex(ir_idex), + .A_idex(A_idex), + .B_idex(B_idex), + .RegWrite_idex(RegWrite_idex), + .MemtoReg_idex(MemtoReg_idex), + .Branch_idex(Branch_idex), + .MemRead_idex(MemRead_idex), + .RegDst_idex(RegDst_idex), + .ALUOp_idex(ALUOp_idex), + .ALUSrc_idex(ALUSrc_idex), + .Jump_idex(Jump_idex), + + .npc_exmem(npc_exmem), + .ir_exmem(ir_exmem), + .Y_exmem(Y_exmem), + .imm_exmem(imm_exmem), + .RegWrite_exmem(RegWrite_exmem), + .MemtoReg_exmem(MemtoReg_exmem), + .Branch_exmem(Branch_exmem), + .MemWrite_exmem(MemWrite_exmem), + .MemRead_exmem(MemRead_exmem), + .MemWrite_idex(MemWrite_idex), + .Jump_exmem(Jump_exmem), + + .MDR_memwb(MDR_memwb), + .ir_memwb(ir_memwb), + .Y_memwb(Y_memwb), + .WA_memwb(WA_memwb), + .RegWrite_memwb(RegWrite_memwb), + .MemtoReg_memwb(MemtoReg_memwb), + + .m_rf_addr(m_rf_addr), + .rf_data(rf_data), + .m_data(m_data) + ); + //always @ (posedge clk) + //dclk = ~dclk; + + always @ (posedge clk) begin + if (rst) begin + m_rf_addr <= 0; + //dclk <= 0; + dclk <= ~dclk; + led <= 16'b0; + step_real_old <= 0; + end + else begin + if (succ == 1) begin dclk <= !dclk; end + else begin + if (step_real) dclk <= !dclk; + else if (step_real_old) dclk <= !dclk; + end + + step_real_old <= step_real; + + if (inc_real) m_rf_addr <= m_rf_addr + 1; + else if (dec_real) m_rf_addr <= m_rf_addr - 1; + + if (sel == 3'b0) + led <= {7'b0, m_rf_addr}; + else begin + case (sel) + 3: led <= {RegWrite_idex, MemtoReg_idex, Branch_idex, MemRead_idex, MemWrite_idex, RegDst_idex, ALUOp_idex, ALUSrc_idex, Jump_idex, 5'b0}; + 4: led <= {RegWrite_exmem, MemtoReg_exmem, Branch_exmem, MemRead_exmem, MemWrite_exmem, 0, 3'b000, 0, Jump_exmem, 5'b0}; + 5: led <= {RegWrite_memwb, MemtoReg_memwb, 0, 0, 0, 0, 3'b000, 0, 0, 5'b0}; + default: led <= 16'hFF; + endcase + end + + case (sel) + 0: begin + if (m_rf == 1) seg_data <= m_data; else seg_data <= rf_data; + end + 1: seg_data <= pc; + 2: case (sel2) + 0: seg_data <= npc_ifid; + 1: seg_data <= ir_ifid; + default: seg_data <= 0; + endcase + 3: case (sel2) + 0: seg_data <= npc_idex; + 1: seg_data <= ir_idex; + 2: seg_data <= A_idex; + 3: seg_data <= B_idex; + endcase + 4: case (sel2) + 0: seg_data <= npc_exmem; + 1: seg_data <= ir_exmem; + 2: seg_data <= Y_exmem; + 3: seg_data <= imm_exmem; + endcase + 5: case (sel2) + 0: seg_data <= MDR_memwb; + 1: seg_data <= ir_memwb; + 2: seg_data <= Y_memwb; + 3: seg_data <= WA_memwb; + endcase + default: seg_data <= 32'b0; + endcase + end + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/register_file.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/register_file.v" new file mode 100755 index 0000000..875b5d8 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/register_file.v" @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +// regfile with debug port and fowarding -- write & read in same cycle +// 2020 COD Lab5 +// ustcpetergu + +module register_file + #(parameter WIDTH = 32) + ( + input clk, + input [4:0]ra0, + input [4:0]ra1, + input [4:0]ra2, + input [4:0]wa, + input we, + input [WIDTH-1:0]wd, + output reg [WIDTH-1:0]rd0, + output reg [WIDTH-1:0]rd1, + output reg [WIDTH-1:0]rd2 + ); + + reg [WIDTH-1:0]regfile[31:0]; + initial $readmemh("/home/petergu/MyHome/COD/lab4/regfile.dat", regfile); + + always @ (*) begin + if (ra0 == 5'b0) rd0 = 0; + else if (we & (ra0 == wa)) rd0 = wd; + else rd0 = regfile[ra0]; + + if (ra1 == 5'b0) rd1 = 0; + else if (we & (ra1 == wa)) rd1 = wd; + else rd1 = regfile[ra1]; + + if (ra2 == 5'b0) rd2 = 0; + else if (we & (ra2 == wa)) rd2 = wd; + else rd2 = regfile[ra2]; + end + + always @ (posedge clk) begin + if (we) begin + if (wa != 5'b0) begin + regfile[wa] <= wd; + end + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/seven-segment.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/seven-segment.v" new file mode 100644 index 0000000..5ff5af9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/seven-segment.v" @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps +// 7-segment digital control +// 2020 COD Lab +// ustcpetergu + +module seven_segment + ( + input clk, + input rst, + input [31:0]x, + output reg [7:0]an, + output reg [6:0]seg + ); + reg [31:0]count = 0; + localparam UPDATE_COUNT = 100000; + reg [2:0]select = 0; + reg [3:0]x0; + always @ (*) begin + case (select) + 0: begin x0 = x[3:0]; an = 8'b11111110; end + 1: begin x0 = x[7:4]; an = 8'b11111101; end + 2: begin x0 = x[11:8]; an = 8'b11111011; end + 3: begin x0 = x[15:12]; an = 8'b11110111; end + 4: begin x0 = x[19:16]; an = 8'b11101111; end + 5: begin x0 = x[23:20]; an = 8'b11011111; end + 6: begin x0 = x[27:24]; an = 8'b10111111; end + 7: begin x0 = x[31:28]; an = 8'b01111111; end + default: begin x0 = 0; an = 0; end + endcase + case (x0) + // +7+ + // 2 6 + // +1+ + // 3 5 + // +4+ + 0: seg = 7'b1000000; + 1: seg = 7'b1111001; + 2: seg = 7'b0100100; + 3: seg = 7'b0110000; + 4: seg = 7'b0011001; + 5: seg = 7'b0010010; + 6: seg = 7'b0000010; + 7: seg = 7'b1111000; + 8: seg = 7'b0000000; + 9: seg = 7'b0010000; + 10: seg = 7'b0001000; + 11: seg = 7'b0000011; + 12: seg = 7'b1000110; + 13: seg = 7'b0100001; + 14: seg = 7'b0000110; + 15: seg = 7'b0001110; + default: seg = 0; + endcase + end + always @ (posedge clk) begin + if (rst) + count <= 0; + else if (count >= UPDATE_COUNT) begin + count <= 0; + select <= select + 1; + end else + count <= count + 1; + end +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/top_test.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/top_test.v" new file mode 100644 index 0000000..4cc8bd6 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/top_test.v" @@ -0,0 +1,240 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 06/15/2020 10:25:51 AM +// Design Name: +// Module Name: top_test +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module top_test + ( + input clk, + input rst, + + output reg [15:0]led = 0, + output wire [7:0]an, + output wire [6:0]seg, + + output reg [31:0]seg_data = 0 + ); + + + reg succ = 1; + reg step = 0; + reg [2:0]sel = 0; + reg [1:0]sel2 = 0; + reg m_rf = 0; + reg inc = 0; + reg dec = 0; + + seven_segment seven_segment_inst + ( + .clk(clk), + .rst(rst), + .x(seg_data), + .an(an), + .seg(seg) + ); + + //wire step_real; + //reg step_real_old = 0; + //wire inc_real; + //wire dec_real; + + reg step_real = 0; + reg step_real_old = 0; + reg inc_real = 0; + reg dec_real = 0; + + //edgefetcher_0 edgefetcher_inst_0 + //( + //.clk(clk), + //.rst(rst), + //.y(step), + //.p(step_real) + //); + //edgefetcher_0 edgefetcher_inst_1 + //( + //.clk(clk), + //.rst(rst), + //.y(inc), + //.p(inc_real) + //); + //edgefetcher_0 edgefetcher_inst_2 + //( + //.clk(clk), + //.rst(rst), + //.y(dec), + //.p(dec_real) + //); + + reg dclk = 0; + reg [7:0]m_rf_addr = 0; + wire [31:0]m_data; + wire [31:0]rf_data; + + wire [31:0]pc; + + wire [31:0]npc_ifid; + wire [31:0]ir_ifid; + + wire [31:0]npc_idex; + wire [31:0]ir_idex; + wire [31:0]A_idex; + wire [31:0]B_idex; + wire RegWrite_idex; + wire MemtoReg_idex; + wire Branch_idex; + wire MemRead_idex; + wire RegDst_idex; + wire [2:0]ALUOp_idex; + wire ALUSrc_idex; + wire Jump_idex; + + wire [31:0]npc_exmem; + wire [31:0]ir_exmem; + wire [31:0]Y_exmem; + wire [31:0]imm_exmem; + wire RegWrite_exmem; + wire MemtoReg_exmem; + wire Branch_exmem; + wire MemWrite_exmem; + wire MemRead_exmem; + wire MemWrite_idex; + wire Jump_exmem; + + wire [31:0]MDR_memwb; + wire [31:0]ir_memwb; + wire [31:0]Y_memwb; + wire [31:0]WA_memwb; + wire RegWrite_memwb; + wire MemtoReg_memwb; + + cpu_pipeline cpu_pipeline_inst + ( + .clk(dclk), + .rst(rst), + + .pc(pc), + + .npc_ifid(npc_ifid), + .ir_ifid(ir_ifid), + + .npc_idex(npc_idex), + .ir_idex(ir_idex), + .A_idex(A_idex), + .B_idex(B_idex), + .RegWrite_idex(RegWrite_idex), + .MemtoReg_idex(MemtoReg_idex), + .Branch_idex(Branch_idex), + .MemRead_idex(MemRead_idex), + .RegDst_idex(RegDst_idex), + .ALUOp_idex(ALUOp_idex), + .ALUSrc_idex(ALUSrc_idex), + .Jump_idex(Jump_idex), + + .npc_exmem(npc_exmem), + .ir_exmem(ir_exmem), + .Y_exmem(Y_exmem), + .imm_exmem(imm_exmem), + .RegWrite_exmem(RegWrite_exmem), + .MemtoReg_exmem(MemtoReg_exmem), + .Branch_exmem(Branch_exmem), + .MemWrite_exmem(MemWrite_exmem), + .MemRead_exmem(MemRead_exmem), + .MemWrite_idex(MemWrite_idex), + .Jump_exmem(Jump_exmem), + + .MDR_memwb(MDR_memwb), + .ir_memwb(ir_memwb), + .Y_memwb(Y_memwb), + .WA_memwb(WA_memwb), + .RegWrite_memwb(RegWrite_memwb), + .MemtoReg_memwb(MemtoReg_memwb), + + .m_rf_addr(m_rf_addr), + .rf_data(rf_data), + .m_data(m_data) + ); + + //always @ (posedge clk) + //dclk = ~dclk; + + always @ (posedge clk) begin + if (rst) begin + m_rf_addr <= 0; + //dclk <= 0; + dclk <= ~dclk; + led <= 16'b0; + step_real_old <= 0; + end + else begin + if (succ == 1) begin dclk <= !dclk; end + else begin + if (step_real) dclk <= !dclk; + else if (step_real_old) dclk <= !dclk; + end + + step_real_old <= step_real; + + if (inc_real) m_rf_addr <= m_rf_addr + 1; + else if (dec_real) m_rf_addr <= m_rf_addr - 1; + + if (sel == 3'b0) + led <= {7'b0, m_rf_addr}; + else begin + case (sel) + 3: led <= {RegWrite_idex, MemtoReg_idex, Branch_idex, MemRead_idex, MemWrite_idex, RegDst_idex, ALUOp_idex, ALUSrc_idex, Jump_idex, 5'b0}; + 4: led <= {RegWrite_exmem, MemtoReg_exmem, Branch_exmem, MemRead_exmem, MemWrite_exmem, 0, 3'b000, 0, Jump_exmem, 5'b0}; + 5: led <= {RegWrite_memwb, MemtoReg_memwb, 0, 0, 0, 0, 3'b000, 0, 0, 5'b0}; + default: led <= 16'hFF; + endcase + end + + case (sel) + 0: begin + if (m_rf == 1) seg_data <= m_data; else seg_data <= rf_data; + end + 1: seg_data <= pc; + 2: case (sel2) + 0: seg_data <= npc_ifid; + 1: seg_data <= ir_ifid; + default: seg_data <= 0; + endcase + 3: case (sel2) + 0: seg_data <= npc_idex; + 1: seg_data <= ir_idex; + 2: seg_data <= A_idex; + 3: seg_data <= B_idex; + endcase + 4: case (sel2) + 0: seg_data <= npc_exmem; + 1: seg_data <= ir_exmem; + 2: seg_data <= Y_exmem; + 3: seg_data <= imm_exmem; + endcase + 5: case (sel2) + 0: seg_data <= MDR_memwb; + 1: seg_data <= ir_memwb; + 2: seg_data <= Y_memwb; + 3: seg_data <= WA_memwb; + endcase + default: seg_data <= 32'b0; + endcase + end + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5.tcl" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5.tcl" new file mode 100644 index 0000000..7717501 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/lab5.tcl" @@ -0,0 +1,594 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1 (64-bit) +# +# lab5.tcl: Tcl script for re-creating project 'lab5-cpu-pipeline' +# +# Generated by Vivado on Thu Jun 25 19:50:36 CST 2020 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (lab5.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/cpu-pipeline.v" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/register_file.v" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/seven-segment.v" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/pipeline_dbu.v" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/alu_0/alu_0.xci" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_1/dist_mem_gen_1.xci" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/cpu_pipeline_simu.v" +# "/home/petergu/MyHome/COD/lab5/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/pipeline_dbu_simu.v" +# +# 3. The following remote source files that were added to the original project:- +# +# "/home/petergu/MyHome/COD/lab5/ins_2.coe" +# "/home/petergu/MyHome/COD/lab5/data_2.coe" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "lab5-cpu-pipeline" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "lab5.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/lab5-cpu-pipeline"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "www.digilentinc.com:pynq-z1:part0:1.0" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "pynq-z1" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "18" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "18" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "18" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "18" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "18" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "18" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "18" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "82" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/ins_2.coe"] \ + [file normalize "${origin_dir}/data_2.coe"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/cpu-pipeline.v" ]\ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/register_file.v" ]\ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/seven-segment.v" ]\ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/new/pipeline_dbu.v" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "pipeline_dbu" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/alu_0/alu_0.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "alu_0/alu_0.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "dist_mem_gen_0/dist_mem_gen_0.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sources_1/ip/dist_mem_gen_1/dist_mem_gen_1.xci" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "dist_mem_gen_1/dist_mem_gen_1.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Empty (no sources present) + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/cpu_pipeline_simu.v" ]\ + [file normalize "${origin_dir}/lab5-cpu-pipeline/lab5-cpu-pipeline.srcs/sim_1/new/pipeline_dbu_simu.v" ]\ +] +set imported_files [import_files -fileset sim_1 $files] + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "nl.mode" -value "funcsim" -objects $obj +set_property -name "top" -value "cpu_pipeline_simu" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "xsim.simulate.log_all_signals" -value "1" -objects $obj +set_property -name "xsim.simulate.saif_all_signals" -value "1" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z020clg400-1 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z020clg400-1 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/logic.png" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/logic.png" new file mode 100644 index 0000000..2ad9cdc Binary files /dev/null and "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/logic.png" differ diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/report.md" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/report.md" new file mode 100644 index 0000000..0edb7ab --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/report.md" @@ -0,0 +1,511 @@ +## Lab5 流水线CPU + +古宜民 PB17000002 + +2020.6.25 + +### CPU + +**寄存器堆** + +为了支持充足的转发寄存器堆必须支持一个周期内先写后读，这里使用了寄存器堆内的转发实现这一功能，而真正写入依旧等到下一个时钟上升沿。 + +**数据通路** + +数据通路基于文档上的逻辑图： + +![](logic.png) + +除了给出的内容外，还要加上ADDI，JUMP指令的数据通路。BEQ和JUMP指令未进行提前，仍然在MEM段完成。 + +另外，除了处理Control Unit给出的控制信号之外，还要处理转发和冒险单元给出的信号，加入从后到前数据的通路和流水线寄存器清空插入气泡的功能。 + +时序部分，每个周期需要更新各个段寄存器的值。无转发时新的值来自上一段的计算结果，而发生转发（信号exmem2ALUA，exmem2ALUB，memwb2ALUA，memwb2ALUB，exmem2DataMem，memwb2DataMem，来自转发单元）时新的值可能来自本段或其之后的段。有气泡时（信号nPCWrite，nIFIDWrite，来自冒险检测单元）PC将不会更新，重新取一次当前指令。发生跳转时清零流水线（Flush，来自控制单元），将过去计算完成的结果清零。 + +```verilog + always @ (*) begin + // with forwarding + if (exmem2ALUA) ALUa = Y_exmem; + else if (memwb2ALUA) ALUa = WriteData; + else ALUa = A_idex; + end + always @ (*) begin + // with forwarding + if (exmem2ALUB) ALUb = Y_exmem; + else if (memwb2ALUB) ALUb = WriteData; + else if (ALUSrc_idex) ALUb = imm_idex; + else ALUb = B_idex; + end + always @ (*) begin + if (MemtoReg_memwb) WriteData = MDR_memwb; + else WriteData = Y_memwb; + end + always @ (posedge clk) begin + if (rst) begin + ... + end + else begin + // pc + // with interlock + if (nPCWrite == 0) begin + if (Jump_exmem) pc <= {4'b0000, ir_exmem[25:0], 2'b00}; + else if (PCSrc) pc <= npc_exmem; + else pc <= pc + 4; + end + + // data -- ifid + // with interlock + if (Flush) begin + npc_ifid <= 0; + ir_ifid <= 0; + end + else if (nIFIDWrite == 0) begin + npc_ifid <= pc + 4; + ir_ifid <= instruction; + end + + // data -- idex + if (Flush) begin + npc_idex <= 0; + A_idex <= 0; + B_idex <= 0; + imm_idex <= 0; + ir_ifid <= 0; + end + else begin + npc_idex <= npc_ifid; + A_idex <= ReadData1; + B_idex <= ReadData2; + imm_idex <= {{16{ir_ifid[15]}}, ir_ifid[15:0]}; + ir_idex <= ir_ifid; + end + + // data -- exmem + // this flush is actually unnecessary + if (Flush) begin + npc_exmem <= 0; + ZF_exmem <= 0; + Y_exmem <= 0; + imm_idex <= 0; + WA_exmem <= 0; + B_exmem <= 0; + end + else begin + npc_exmem <= npc_idex + (imm_idex << 2); + ZF_exmem <= ALUZero; + Y_exmem <= ALUy; + imm_exmem <= imm_idex; + if (RegDst_idex) WA_exmem <= ir_idex[15:11]; + else WA_exmem <= ir_idex[20:16]; + ir_exmem <= ir_idex; + // with forwarding + if (exmem2DataMem) B_exmem <= Y_exmem; + else B_exmem <= B_idex; + end + + // data -- memwb + MDR_memwb <= ReadData_ram; + Y_memwb <= Y_exmem; + WA_memwb <= WA_exmem; + ir_memwb <= ir_exmem; + end + end +``` + +**控制信号** + +类似于单周期CPU的控制信号，每条指令对应的控制信号在ID段生成，并需要每个周期传到下一段。如果流水线需要插入气泡则控制单元给出一个周期的全0信号。 + +代码如下，其中Flush在发生跳转（JUMP或BEQ选中）时生成，nControl来自冒险检测单元。 + +```verilog + // control unit + assign PCSrc = ZF_exmem & Branch_exmem; + assign Flush = Jump_exmem | PCSrc; + reg RegWrite; + reg MemtoReg; + reg Branch; + reg MemRead; + reg MemWrite; + reg RegDst; + reg ALUOp; + reg ALUSrc; + reg Jump; + always @ (*) begin + RegWrite = 0; + MemtoReg = 0; + Branch = 0; + MemRead = 0; + MemWrite = 0; + RegDst = 0; + ALUOp = 3'b0; + ALUSrc = 0; + Jump = 0; + case (ir_ifid[31:26]) + 6'b000000: + case (ir_ifid[5:0]) + // add--- --rs- --rt- --rd- shamt funct- + 6'b100000: begin RegDst = 1; RegWrite = 1; end + default: ; + endcase + // addi-- --rs- --rt- ----immediate--- + 6'b001000: begin ALUSrc = 1; RegWrite = 1; end + // lw---- --rs- --rt- ----addr-------- + 6'b100011: begin ALUSrc = 1; RegWrite = 1; MemRead = 1; MemtoReg = 1; end + // sw---- --rs- --rt- ----addr-------- + 6'b101011: begin ALUSrc = 1; MemWrite = 1; end + // beq-- --rs- --rt- ----addr-------- + 6'b000100: begin Branch = 1; ALUOp = 3'b001; end + // j---- ----addr------------------ + 6'b000010: begin Jump = 1; end + default: ; + endcase + end + always @ (posedge clk) begin + if (rst) begin + ... + end + else begin + // control -- idex + if (nControl == 0 & Flush== 0) begin + RegWrite_idex <= RegWrite; + MemtoReg_idex <= MemtoReg; + Branch_idex <= Branch; + MemRead_idex <= MemRead; + MemWrite_idex <= MemWrite; + RegDst_idex <= RegDst; + ALUOp_idex <= ALUOp; + ALUSrc_idex <= ALUSrc; + Jump_idex <= Jump; + end + else begin + RegWrite_idex <= 0; + MemtoReg_idex <= 0; + Branch_idex <= 0; + MemRead_idex <= 0; + MemWrite_idex <= 0; + RegDst_idex <= 0; + ALUOp_idex <= 3'b0; + ALUSrc_idex <= 0; + Jump_idex <= 0; + end + + // control -- exmem + // this flush is actually unnecessary + if (Flush) begin + RegWrite_exmem <= 0; + MemtoReg_exmem <= 0; + Branch_exmem <= 0; + MemRead_exmem <= 0; + MemWrite_exmem <= 0; + Jump_exmem <= 0; + end + else begin + RegWrite_exmem <= RegWrite_idex; + MemtoReg_exmem <= MemtoReg_idex; + Branch_exmem <= Branch_idex; + MemRead_exmem <= MemRead_idex; + MemWrite_exmem <= MemWrite_idex; + Jump_exmem <= Jump_idex; + end + + // control -- memwb + RegWrite_memwb <= RegWrite_exmem; + MemtoReg_memwb <= MemtoReg_exmem; + end + end +``` + +**转发** + +如代码注释，以下各种情况都需要转发：exmem段的ALUOut、memwb段的ALUOut、memwb段的MDR分别转发到ALU的两个输入（ALUInA，ALUInB）以及内存写入的数据（DataMemory，无转发时为B_exmem） + +``` + // ADDI + LW + // ADDI + SW(ex) + // ADDI + ADDI + // ADDI + R(A) + // ADDI + BEQ(A) + // exmem(ALUOut) to ALUIn A + // ADDI + R(B) + // ADDI + BEQ(B) + // exmem(ALUOut) to ALUIn B + + // R + LW + // R + SW(ex) + // R + ADDI + // R + R(A) + // R + BEQ(A) + // exmem(ALUOut) to ALUIn A + // R + R(B) + // R + BEQ(B) + // exmem(ALUOut) to ALUIn B + + // LW + * + LW + // LW + * + SW(wb) + // LW + * + ADDI + // LW + * + R(A) + // LW + * + BEQ(A) + // ADDI + * + LW + // ADDI + * + SW(ex) + // ADDI + * + ADDI + // ADDI + * + R(A) + // ADDI + * + BEQ(A) + // memwb(ALUOut or MDR) to ALUIn A + // LW + * + R(B) + // LW + * + BEQ(B) + // ADDI + * + R(B) + // ADDI + * + BEQ(B) + // memwb(ALUOut or MDR) to ALUIn B + + // R + * + LW + // R + * + SW(ex) + // R + * + ADDI + // R + * + R(A) + // R + * + BEQ(A) + // memwb(ALUOut) to ALUIn A + // R + * + R(B) + // R + * + BEQ(B) + // memwb(ALUOut) to ALUIn B + + // R + SW(wb) + // exmem(ALUOut) to DataMemory(B_exmem) + // R + * + SW(wb) + // memwb(ALUOut) to DataMemory(B_exmem) + // LW + SW(wb) + // memwb(MDR) to DataMemory(B_exmem) +``` + +而转发的条件是ID/EX段的指令（接受转发）与EX/MEM或MEM/WB（来源）指令的操作寄存器有一定相同，需要针对每种情况进行判断和发出信号，较为繁杂。注意如果寄存器是0，则写入无效，所以转发会引发错误，所以针对寄存器为0的情况特殊判断。 + +代码： + +```verilog + // forwarding unit + reg exmem2ALUA; + reg exmem2ALUB; + reg exmem2DataMem; + reg memwb2ALUA; + reg memwb2ALUB; + reg memwb2DataMem; + always @ (*) begin + exmem2ALUA = 0; + exmem2ALUB = 0; + exmem2DataMem = 0; + memwb2ALUA = 0; + memwb2ALUB = 0; + memwb2DataMem = 0; + + // ADDI + LW + // ADDI + SW(ex) + // ADDI + ADDI + // ADDI + R(A) + // ADDI + BEQ(A) + // exmem(ALUOut) to ALUIn A + // ADDI + R(B) + // ADDI + BEQ(B) + // exmem(ALUOut) to ALUIn B + if ((ir_exmem[31:26] == 6'b001000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[20:16] != 5'b0 & ir_exmem[20:16] == ir_idex[25:21]) exmem2ALUA = 1; + if ((ir_exmem[31:26] == 6'b001000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[20:16] != 5'b0 & ir_exmem[20:16] == ir_idex[20:16]) exmem2ALUB = 1; + + // R + LW + // R + SW(ex) + // R + ADDI + // R + R(A) + // R + BEQ(A) + // exmem(ALUOut) to ALUIn A + // R + R(B) + // R + BEQ(B) + // exmem(ALUOut) to ALUIn B + if ((ir_exmem[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[15:11] != 5'b0 & ir_exmem[15:11] == ir_idex[25:21]) exmem2ALUA = 1; + if ((ir_exmem[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_exmem[15:11] != 5'b0 & ir_exmem[15:11] == ir_idex[20:16]) exmem2ALUB = 1; + + // LW + * + LW + // LW + * + SW(wb) + // LW + * + ADDI + // LW + * + R(A) + // LW + * + BEQ(A) + // ADDI + * + LW + // ADDI + * + SW(ex) + // ADDI + * + ADDI + // ADDI + * + R(A) + // ADDI + * + BEQ(A) + // memwb(ALUOut or MDR) to ALUIn A + // LW + * + R(B) + // LW + * + BEQ(B) + // ADDI + * + R(B) + // ADDI + * + BEQ(B) + // memwb(ALUOut or MDR) to ALUIn B + if ((ir_memwb[31:26] == 6'b100011 | ir_memwb[31:26] == 6'b001000 | ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[20:16] != 5'b0 & ir_memwb[20:16] == ir_idex[25:21]) memwb2ALUA = 1; + if ((ir_memwb[31:26] == 6'b100011 | ir_memwb[31:26] == 6'b001000 | ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[20:16] != 5'b0 & ir_memwb[20:16] == ir_idex[20:16]) memwb2ALUB = 1; + // R + * + LW + // R + * + SW(ex) + // R + * + ADDI + // R + * + R(A) + // R + * + BEQ(A) + // memwb(ALUOut) to ALUIn A + // R + * + R(B) + // R + * + BEQ(B) + // memwb(ALUOut) to ALUIn B + if ((ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b100011 | ir_idex[31:26] == 6'b101011 | ir_idex[31:26] == 6'b001000 | ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[15:11] != 5'b0 & ir_memwb[15:11] == ir_idex[25:21]) memwb2ALUA = 1; + if ((ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b000000 | ir_idex[31:26] == 6'b000100) & + ir_memwb[15:11] != 5'b0 & ir_memwb[15:11] == ir_idex[20:16]) memwb2ALUB = 1; + + // R + SW(wb) + // exmem(ALUOut) to DataMemory(B_exmem) + // R + * + SW(wb) + // memwb(ALUOut) to DataMemory(B_exmem) + // LW + SW(wb) + // memwb(MDR) to DataMemory(B_exmem) + if ((ir_exmem[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b101011) & + ir_exmem[15:11] != 5'b0 & ir_exmem[15:11] == ir_idex[20:16]) exmem2DataMem = 1; + if ((ir_memwb[31:26] == 6'b000000) & + (ir_idex[31:26] == 6'b101011) & + ir_memwb[15:11] != 5'b0 & ir_memwb[15:11] == ir_idex[20:16]) memwb2DataMem = 1; + if ((ir_memwb[31:26] == 6'b100011) & + (ir_idex[31:26] == 6'b101011) & + ir_memwb[20:16] != 5'b0 & ir_memwb[20:16] == ir_idex[20:16]) exmem2DataMem = 1; + + end +``` + +**冒险检测** + +对于以下情况： + +``` + // LW + R(A, B) + // LW + LW + // LW + ADDI + // LW + SW(ex) + // LW + BEQ(A, B) +``` + +LW的下一条指令无法通过转发获得需要的值，必须停顿一个周期，不更新PC，不进行指令译码，控制信号置0。同样0号寄存器特殊处理。 + +```verilog + // hazard detection unit + reg nPCWrite; + reg nIFIDWrite; + reg nControl; + always @ (*) begin + // LW + R(A, B) + // LW + LW + // LW + ADDI + // LW + SW(ex) + // LW + BEQ(A, B) + // stall + if (ir_idex[31:26] == 6'b100011 & ( + (ir_idex[20:16] != 5'b0 & ir_idex[20:16] == ir_ifid[25:21] & (ir_ifid[31:26] == 6'b000000 | ir_ifid[31:26] == 6'b100011 | ir_ifid[31:26] == 6'b001000 | ir_ifid[31:26] == 6'b101011 | ir_ifid[31:26] == 6'b000100)) | + (ir_idex[20:16] != 5'b0 & ir_idex[20:16] == ir_ifid[20:16] & (ir_ifid[31:26] == 6'b000000 | ir_ifid[31:26] == 6'b000100)) + )) begin + nPCWrite = 1; + nIFIDWrite = 1; + nControl = 1; + end + else begin + nPCWrite = 0; + nIFIDWrite = 0; + nControl = 0; + end + end +``` + + + +**仿真结果** + +使用助教提供的程序： + +```asm +# Test cases for MIPS 5-Stage pipeline + +.data + .word 0,1,2,3,0x80000000,0x80000100,0x100,5,0 + +_start: + add $t1, $0, $0 # $t1 = 0 # 0 + j _test0 + +_test0: + addi $t2, $0, 1 # $t2 = 1 # 8 + addi $t2, $t2, 1 # $t2 = 2 + add $t2, $t2, $t2 # $t2 = 4 + addi $t2, $t2, -4 # $t2 = 0 + beq $t2, $0, _next0 # if $t2 == $0: $t1++, go next testcase, else: go fail + j _fail +_next0: + addi $t1, $t1, 1 # $t1++ # 32 + j _test1 + +_test1: + addi $0, $0, 4 # $0 += 4 # 40 + lw $t2, 4($0) # $t2 = MEM[1] + lw $t3, 8($0) # $t3 = MEM[2] + add $t4, $t2, $t3 + sw $t4, 0($0) # MEM[0] = $t4 + lw $t5, 0($0) # $t5 = MEM[0] + lw $t6, 12($0) # $t6 = MEM[3] + beq $t5, $t6, _next1 + j _fail + +_next1: + addi $t1, $t1, 1 # 76 + j _success + +_fail: + j _fail + +_success: + j _success # if success: $t1 == 2 # 88 +``` + +例如第一条指令的执行过程： + +![](1.png) + +为了节省空间删去了一些段的控制信号。可见指令0x00004820分别经过IFID、IDEX、EXMEM、MEMWB段寄存器，在WB段RegWrite=1写回，下一个时钟上升沿regfile发生变化，查看发现确实是其中第9个寄存器被写入了0. + +冒险检测的例子： + +对这三条指令： + +```asm + lw $t2, 4($0) # $t2 = MEM[1] + lw $t3, 8($0) # $t3 = MEM[2] + add $t4, $t2, $t3 +``` + +执行如图： + +![](2.png) + +0x8c0开头为两条LW，0x14b6020为ADD。可见ADD译码后检测到了冒险，nPCWrite、nIFIDWrite、nControl被置1，进而停顿一个周期，下一个周期再次取指令0x14b6020，这次可以通过转发解决冒险，信号memwb2ALUA为1发生了转发。 + +最后可见寄存器堆中各寄存器和预期相同： + +![](3.png) + +### 总结 + +流水线CPU编写和调试较为困难，尤其是转发和冒险单元，一不小心就会对于某条或某几条指令产生错误，需要反复仔细调试。对于ADDI和JUMP指令文档中没有给出现成的数据通路，也使得设计增加了一些难度。关于冒险和转发，目前程序中的写法有些罗嗦，如果指令增加那么转发代码量会平方增加，需要使用更简洁的写法。 + +完整代码在http://home.ustc.edu.cn/~guyimin/Legacy/lab5.tar.gz + +sha1:ec774d136f9258be2d5782793b60c670ad8f6c75 \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/test_1.asm" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/test_1.asm" new file mode 100644 index 0000000..fdc2918 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/test_1.asm" @@ -0,0 +1,45 @@ +# 本文档存储器以字节编址 +# 本文档存储器以字节编址 +# 本文档存储器以字节编址 +# 初始PC = 0x00000000 + +.data + .word 0,6,0,16,0x80000000,0x80000100,0x100,5,0 #编译成机器码时，编译器会在前面多加个0，所以后面lw指令地址会多加4 + +_start: + addi $t0,$0,3 #t0=3 0 + addi $t1,$t0,2 #t1=5 4 + addi $t2,$0,1 #t2=1 8 + addi $t3,$0,0 #t3=0 12 + + add $s0,$t1,$t0 #s0=t1+t0=8 测试add指令 16 + add $s0,$s0,$s0 #s0=s0+s0=16 20 + lw $s1,12($0) # 24 + beq $s1,$s0,_next1 #正确跳到_next 28 + + j _fail + +_next1: + lw $t0, 16($0) #t0 = 0x80000000 36 + lw $t1, 20($0) #t1 = 0x80000100 40 + + add $s0,$t1,$t0 #s0 = 0x00000100 = 256 44 + lw $s1, 24($0) # 48 + beq $s1,$s0,_next2 #正确跳到_success 52 + + j _fail + +_next2: + add $0, $0, $t2 #$0应该一直为0 60 + beq $0,$t3,_success # 64 + + +_fail: + sw $t3,8($0) #失败通过看存储器地址0x08里值，若为0则测试不通过，最初地址0x08里值为0 64 68? + j _fail 68 72? + +_success: + sw $t2,8($0) #全部测试通过，存储器地址0x08里值为1 72 76? + j _success 76 80? + + #判断测试通过的条件是最后存储器地址0x08里值为1，说明全部通过测试 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/test_2.asm" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/test_2.asm" new file mode 100644 index 0000000..6c70e09 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab5/test_2.asm" @@ -0,0 +1,40 @@ +# Test cases for MIPS 5-Stage pipeline + +.data + .word 0,1,2,3,0x80000000,0x80000100,0x100,5,0 + +_start: + add $t1, $0, $0 # $t1 = 0 # 0 + j _test0 + +_test0: + addi $t2, $0, 1 # $t2 = 1 # 8 + addi $t2, $t2, 1 # $t2 = 2 + add $t2, $t2, $t2 # $t2 = 4 + addi $t2, $t2, -4 # $t2 = 0 + beq $t2, $0, _next0 # if $t2 == $0: $t1++, go next testcase, else: go fail + j _fail +_next0: + addi $t1, $t1, 1 # $t1++ # 32 + j _test1 + +_test1: + addi $0, $0, 4 # $0 += 4 # 40 + lw $t2, 4($0) # $t2 = MEM[1] + lw $t3, 8($0) # $t3 = MEM[2] + add $t4, $t2, $t3 + sw $t4, 0($0) # MEM[0] = $t4 + lw $t5, 0($0) # $t5 = MEM[0] + lw $t6, 12($0) # $t6 = MEM[3] + beq $t5, $t6, _next1 + j _fail + +_next1: + addi $t1, $t1, 1 # 76 + j _success + +_fail: + j _fail + +_success: + j _success # if success: $t1 == 2 # 88 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/build_with_asmlib.sh" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/build_with_asmlib.sh" new file mode 100755 index 0000000..11d3cc3 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/build_with_asmlib.sh" @@ -0,0 +1,15 @@ +#!/bin/bash +# usage ./build_with_lib.sh asm_file_name +set -e + +mipsel-linux-gnu-as $1.asm -o $1.o -EB -O0 +mipsel-linux-gnu-as ./mylib/mylib.asm -o mylib.o -EB -O0 + +mipsel-linux-gnu-ld -nostdlib --script linker.ld mylib.o $1.o -o $1.elf -EB +mipsel-linux-gnu-objcopy -O binary $1.elf $1.bin +cat > result_$1.coe << EOF +memory_initialization_radix = 16; +memory_initialization_vector = +EOF +xxd -c 4 -p $1.bin >> result_$1.coe +mipsel-linux-gnu-objdump -d $1.elf diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/ebaz4205.xdc" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/ebaz4205.xdc" new file mode 100644 index 0000000..745b2b7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/ebaz4205.xdc" @@ -0,0 +1,56 @@ +#set_property IOSTANDARD LVCMOS33 [get_ports led_g] +#set_property IOSTANDARD LVCMOS33 [get_ports led_r] +set_property IOSTANDARD LVCMOS33 [get_ports {leddata[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {leddata[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rx] +set_property IOSTANDARD LVCMOS33 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS33 [get_ports {btndata[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {btndata[1]}] + +#set_property PACKAGE_PIN W13 [get_ports led_g] +#set_property PACKAGE_PIN W14 [get_ports led_r] +# G20 J18 for 5 6 +# DATA2-15 +set_property PACKAGE_PIN L16 [get_ports {leddata[0]}] +# DATA2-16 +set_property PACKAGE_PIN L19 [get_ports {leddata[1]}] +# DATA2-17 +set_property PACKAGE_PIN M18 [get_ports uart_rx] +# DATA2-18 +set_property PACKAGE_PIN L20 [get_ports uart_tx] +# DATA2-19 +set_property PACKAGE_PIN M20 [get_ports {btndata[0]}] +# DATA2-20 +set_property PACKAGE_PIN L17 [get_ports {btndata[1]}] + +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_GMII_RX_CLK_0] +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_GMII_TX_CLK_0] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENET0_GMII_TX_EN_0[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_GMII_RX_DV_0] + +set_property IOSTANDARD LVCMOS33 [get_ports MDIO_ETHERNET_0_0_mdc] +set_property IOSTANDARD LVCMOS33 [get_ports MDIO_ETHERNET_0_0_mdio_io] + +set_property PACKAGE_PIN U14 [get_ports ENET0_GMII_RX_CLK_0] +set_property PACKAGE_PIN U15 [get_ports ENET0_GMII_TX_CLK_0] +set_property PACKAGE_PIN Y17 [get_ports {enet0_gmii_rxd[3]}] +set_property PACKAGE_PIN V17 [get_ports {enet0_gmii_rxd[2]}] +set_property PACKAGE_PIN V16 [get_ports {enet0_gmii_rxd[1]}] +set_property PACKAGE_PIN Y16 [get_ports {enet0_gmii_rxd[0]}] +set_property PACKAGE_PIN W19 [get_ports {ENET0_GMII_TX_EN_0[0]}] +set_property PACKAGE_PIN W16 [get_ports ENET0_GMII_RX_DV_0] +set_property PACKAGE_PIN Y19 [get_ports {enet0_gmii_txd[3]}] +set_property PACKAGE_PIN V18 [get_ports {enet0_gmii_txd[2]}] +set_property PACKAGE_PIN Y18 [get_ports {enet0_gmii_txd[1]}] +set_property PACKAGE_PIN W18 [get_ports {enet0_gmii_txd[0]}] + +set_property PACKAGE_PIN W15 [get_ports MDIO_ETHERNET_0_0_mdc] +set_property PACKAGE_PIN Y14 [get_ports MDIO_ETHERNET_0_0_mdio_io] diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/echo.asm" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/echo.asm" new file mode 100644 index 0000000..f656d71 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/echo.asm" @@ -0,0 +1,43 @@ +.section .text.boot + +_start: + addi $a0, $zero, 0 + jal led_ctrl + addi $a0, $zero, 'O' + jal uart_putchar + addi $a0, $zero, 'K' + jal uart_putchar + lw $s0, mem_addr +_input: + addi $a0, $zero, '\r' + jal uart_putchar + addi $a0, $zero, '\n' + jal uart_putchar + addi $s1, $zero, 0 # loop variable +_loop_input: + jal uart_getchar + add $t0, $s0, $s1 + sw $v0, 0($t0) + addi $t0, $zero, '\r' + beq $v0, $t0, _print + addi $a0, $zero, '.' + jal uart_putchar + addi $s1, $s1, 4 + j _loop_input +_print: + addi $a0, $zero, '\r' + jal uart_putchar + addi $a0, $zero, '\n' + jal uart_putchar + addi $s1, $zero, 0 +_loop_print: + add $t0, $s0, $s1 + lw $a0, 0($t0) + jal uart_putchar + addi $t0, $zero, '\r' + beq $a0, $t0, _input + addi $s1, $s1, 4 + j _loop_print + +.text + mem_addr: .word 0x10000000 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/component.xml" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/component.xml" new file mode 100644 index 0000000..419f413 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/component.xml" @@ -0,0 +1,500 @@ + + + user.org + user + bd_main + 1.0 + + + CLK.SYSCLK + + + + + + + CLK + + + sysclk + + + + + + FREQ_HZ + 125000000 + + + PHASE + 0.000 + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + bd_main + + xilinx_anylanguagesynthesis_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_xilinx_com_ip_xlslice_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 1446af2b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + bd_main + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xlslice_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 0903a133 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + btndata + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + leddata + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sysclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + uart_rx + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + uart_tx + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + src/bd_main_cpu_multi_cycle_0_0.v + verilogSource + IMPORTED_FILE + + + src/bd_main_gpio_0_0.v + verilogSource + IMPORTED_FILE + + + src/bd_main_mmapper_0_0.v + verilogSource + IMPORTED_FILE + + + src/result_echo.coe + coe + IMPORTED_FILE + + + src/bd_main_uart_0_0.v + verilogSource + IMPORTED_FILE + + + src/bd_main_debounce_0_0.v + verilogSource + IMPORTED_FILE + + + src/alu.v + verilogSource + IMPORTED_FILE + + + src/cpu_control_unit.v + verilogSource + IMPORTED_FILE + + + src/register_file.v + verilogSource + IMPORTED_FILE + + + src/cpu-multi-cycle.v + verilogSource + IMPORTED_FILE + + + src/gpio.v + verilogSource + IMPORTED_FILE + + + src/mmapper.v + verilogSource + IMPORTED_FILE + + + src/bd_main_dist_mem_gen_0_0/bd_main_dist_mem_gen_0_0.xci + xci + IMPORTED_FILE + CELL_NAME_bootrom + + processing_order + early + + + + src/bd_main_dist_mem_gen_0_1/bd_main_dist_mem_gen_0_1.xci + xci + IMPORTED_FILE + CELL_NAME_main_memory + + processing_order + early + + + + src/clock_div_pulse.v + verilogSource + IMPORTED_FILE + + + src/uart.v + verilogSource + IMPORTED_FILE + + + src/debounce.v + verilogSource + IMPORTED_FILE + + + src/bd_main_xlslice_0_0/bd_main_xlslice_0_0.xci + xci + IMPORTED_FILE + CELL_NAME_xlslice_0 + + processing_order + early + + + + src/bd_main_ooc.xdc + xdc + IMPORTED_FILE + SCOPED_TO_REF_bd_main + USED_IN_out_of_context + + + src/bd_main.v + verilogSource + CHECKSUM_ab2d59ad + IMPORTED_FILE + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_xilinx_com_ip_xlslice_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + sim/bd_main_cpu_multi_cycle_0_0.v + verilogSource + IMPORTED_FILE + + + sim/bd_main_gpio_0_0.v + verilogSource + IMPORTED_FILE + + + sim/bd_main_mmapper_0_0.v + verilogSource + IMPORTED_FILE + + + src/result_echo.coe + coe + IMPORTED_FILE + + + sim/bd_main_uart_0_0.v + verilogSource + IMPORTED_FILE + + + sim/bd_main_debounce_0_0.v + verilogSource + IMPORTED_FILE + + + src/alu.v + verilogSource + IMPORTED_FILE + + + src/cpu_control_unit.v + verilogSource + IMPORTED_FILE + + + src/register_file.v + verilogSource + IMPORTED_FILE + + + src/cpu-multi-cycle.v + verilogSource + IMPORTED_FILE + + + src/gpio.v + verilogSource + IMPORTED_FILE + + + src/mmapper.v + verilogSource + IMPORTED_FILE + + + src/bd_main_dist_mem_gen_0_0/bd_main_dist_mem_gen_0_0.xci + xci + IMPORTED_FILE + CELL_NAME_bootrom + + processing_order + early + + + + src/bd_main_dist_mem_gen_0_1/bd_main_dist_mem_gen_0_1.xci + xci + IMPORTED_FILE + CELL_NAME_main_memory + + processing_order + early + + + + src/clock_div_pulse.v + verilogSource + IMPORTED_FILE + + + src/uart.v + verilogSource + IMPORTED_FILE + + + src/debounce.v + verilogSource + IMPORTED_FILE + + + src/bd_main_xlslice_0_0/bd_main_xlslice_0_0.xci + xci + IMPORTED_FILE + CELL_NAME_xlslice_0 + + processing_order + early + + + + sim/bd_main.protoinst + unknown + IMPORTED_FILE + + + sim/bd_main.v + verilogSource + IMPORTED_FILE + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_dist_mem_gen_8_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xlslice_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/bd_main_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + bd_main_v1_0 + + + Component_Name + bd_main_v1_0 + + + + + + zynq + + + /UserIP + + bd_main_v1_0 + IPI + 2 + 2020-07-10T08:28:05Z + + /home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/ip + /home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/ip + /home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/ip + /home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/ip + /home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/ip + + + + + + + 2019.1 + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/alu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/alu.v" new file mode 100755 index 0000000..af53a11 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/alu.v" @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +// ALU +// 2020 COD Lab1 +// ustcpetergu + +module alu + #(parameter WIDTH = 32) + ( + input [2:0]m, // selection + input [WIDTH-1:0]a, b, // input + output [WIDTH-1:0]y, // result + output zf, // zero flag + output cf, // carry out flag: WIDTH bit + output of // overflow flag: WIDTH-1 sign bit + ); + + reg [WIDTH-1:0]regy; + reg regcf; + reg regof; + reg regzf; + assign y = regy; + assign cf = regcf; + assign of = regof; + assign zf = regzf; + // assign zf = (regy == 0); + + always @ (a, b, m) begin + case(m) + 3'b000: begin // add + {regcf, regy} = a + b; + regof = (!a[WIDTH-1] & !b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b001: begin // sub + {regcf, regy} = a - b; + regof = (!a[WIDTH-1] & b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & !b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b010: begin // and + regy = a & b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b011: begin // or + regy = a | b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b100: begin // xor + regy = a ^ b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + default: begin // error + regy = 0; + regzf = 0; + regcf = 0; + regof = 0; + end + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main.v" new file mode 100755 index 0000000..4de7ac1 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main.v" @@ -0,0 +1,116 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019 +//Date : Fri Jul 10 16:25:12 2020 +//Host : petergu-dell running 64-bit Arch Linux +//Command : generate_target bd_main.bd +//Design : bd_main +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "bd_main,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=bd_main,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=8,numReposBlks=8,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=5,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "bd_main.hwdef" *) +module bd_main + (btndata, + leddata, + sysclk, + uart_rx, + uart_tx); + input [1:0]btndata; + output [1:0]leddata; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.SYSCLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.SYSCLK, CLK_DOMAIN bd_main_sysclk, FREQ_HZ 125000000, INSERT_VIP 0, PHASE 0.000" *) input sysclk; + input uart_rx; + output uart_tx; + + wire [31:0]bootrom_spo; + wire [1:0]btndata_1; + wire [31:0]cpu_multi_cycle_0_a; + wire [31:0]cpu_multi_cycle_0_d; + wire cpu_multi_cycle_0_we; + wire [1:0]debounce_0_o_state; + wire [1:0]gpio_0_led; + wire [31:0]gpio_0_spo; + wire [31:0]main_memory_spo; + wire [8:0]mmapper_0_bootm_a; + wire [1:0]mmapper_0_gpio_a; + wire [31:0]mmapper_0_gpio_d; + wire mmapper_0_gpio_we; + wire [8:0]mmapper_0_mainm_a; + wire [31:0]mmapper_0_mainm_d; + wire mmapper_0_mainm_we; + wire [31:0]mmapper_0_spo; + wire [2:0]mmapper_0_uart_a; + wire [31:0]mmapper_0_uart_d; + wire mmapper_0_uart_we; + wire rx_0_1; + wire sysclk_1; + wire [31:0]uart_0_spo; + wire uart_0_tx; + wire [0:0]xlslice_0_Dout; + + assign btndata_1 = btndata[1:0]; + assign leddata[1:0] = gpio_0_led; + assign rx_0_1 = uart_rx; + assign sysclk_1 = sysclk; + assign uart_tx = uart_0_tx; + bd_main_dist_mem_gen_0_0 bootrom + (.a(mmapper_0_bootm_a), + .spo(bootrom_spo)); + bd_main_cpu_multi_cycle_0_0 cpu_multi_cycle_0 + (.a(cpu_multi_cycle_0_a), + .clk(sysclk_1), + .d(cpu_multi_cycle_0_d), + .rst(xlslice_0_Dout), + .spo(mmapper_0_spo), + .we(cpu_multi_cycle_0_we)); + bd_main_debounce_0_0 debounce_0 + (.clk(sysclk_1), + .i_btn(btndata_1), + .o_state(debounce_0_o_state)); + bd_main_gpio_0_0 gpio_0 + (.a(mmapper_0_gpio_a), + .btn(debounce_0_o_state), + .clk(sysclk_1), + .d(mmapper_0_gpio_d), + .led(gpio_0_led), + .rst(xlslice_0_Dout), + .spo(gpio_0_spo), + .we(mmapper_0_gpio_we)); + bd_main_dist_mem_gen_0_1 main_memory + (.a(mmapper_0_mainm_a), + .clk(sysclk_1), + .d(mmapper_0_mainm_d), + .spo(main_memory_spo), + .we(mmapper_0_mainm_we)); + bd_main_mmapper_0_0 mmapper_0 + (.a(cpu_multi_cycle_0_a), + .bootm_a(mmapper_0_bootm_a), + .bootm_spo(bootrom_spo), + .d(cpu_multi_cycle_0_d), + .gpio_a(mmapper_0_gpio_a), + .gpio_d(mmapper_0_gpio_d), + .gpio_spo(gpio_0_spo), + .gpio_we(mmapper_0_gpio_we), + .mainm_a(mmapper_0_mainm_a), + .mainm_d(mmapper_0_mainm_d), + .mainm_spo(main_memory_spo), + .mainm_we(mmapper_0_mainm_we), + .spo(mmapper_0_spo), + .uart_a(mmapper_0_uart_a), + .uart_d(mmapper_0_uart_d), + .uart_spo(uart_0_spo), + .uart_we(mmapper_0_uart_we), + .we(cpu_multi_cycle_0_we)); + bd_main_uart_0_0 uart_0 + (.a(mmapper_0_uart_a), + .clk(sysclk_1), + .d(mmapper_0_uart_d), + .rst(xlslice_0_Dout), + .rx(rx_0_1), + .spo(uart_0_spo), + .tx(uart_0_tx), + .we(mmapper_0_uart_we)); + bd_main_xlslice_0_0 xlslice_0 + (.Din(debounce_0_o_state), + .Dout(xlslice_0_Dout)); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_cpu_multi_cycle_0_0.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_cpu_multi_cycle_0_0.v" new file mode 100755 index 0000000..5e81974 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_cpu_multi_cycle_0_0.v" @@ -0,0 +1,86 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:cpu_multi_cycle:1.0 +// IP Revision: 1 + +(* X_CORE_INFO = "cpu_multi_cycle,Vivado 2019.1" *) +(* CHECK_LICENSE_TYPE = "bd_main_cpu_multi_cycle_0_0,cpu_multi_cycle,{}" *) +(* CORE_GENERATION_INFO = "bd_main_cpu_multi_cycle_0_0,cpu_multi_cycle,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=cpu_multi_cycle,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *) +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module bd_main_cpu_multi_cycle_0_0 ( + clk, + rst, + a, + d, + we, + spo +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN bd_main_sysclk, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) +input wire clk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *) +input wire rst; +output wire [31 : 0] a; +output wire [31 : 0] d; +output wire we; +input wire [31 : 0] spo; + + cpu_multi_cycle inst ( + .clk(clk), + .rst(rst), + .a(a), + .d(d), + .we(we), + .spo(spo) + ); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_debounce_0_0.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_debounce_0_0.v" new file mode 100755 index 0000000..01563f7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_debounce_0_0.v" @@ -0,0 +1,77 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:debounce:1.0 +// IP Revision: 1 + +(* X_CORE_INFO = "debounce,Vivado 2019.1" *) +(* CHECK_LICENSE_TYPE = "bd_main_debounce_0_0,debounce,{}" *) +(* CORE_GENERATION_INFO = "bd_main_debounce_0_0,debounce,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=debounce,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,N=2}" *) +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module bd_main_debounce_0_0 ( + clk, + i_btn, + o_state +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN bd_main_sysclk, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) +input wire clk; +input wire [1 : 0] i_btn; +output wire [1 : 0] o_state; + + debounce #( + .N(2) + ) inst ( + .clk(clk), + .i_btn(i_btn), + .o_state(o_state) + ); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_dist_mem_gen_0_0/bd_main_dist_mem_gen_0_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_dist_mem_gen_0_0/bd_main_dist_mem_gen_0_0.xci" new file mode 100755 index 0000000..3f7d6e1 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_dist_mem_gen_0_0/bd_main_dist_mem_gen_0_0.xci" @@ -0,0 +1,104 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_main_dist_mem_gen_0_0 + + + 9 + 0 + 512 + ./ + zynq + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + bd_main_dist_mem_gen_0_0.mif + 0 + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 32 + bd_main_dist_mem_gen_0_0 + 0 + ce_overrides_sync_controls + ../result_echo.coe + false + false + 32 + 0 + 16 + 512 + non_registered + false + false + non_registered + rom + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + + + xc7z010 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 13 + TRUE + . + + ../../ipshared + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_dist_mem_gen_0_1/bd_main_dist_mem_gen_0_1.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_dist_mem_gen_0_1/bd_main_dist_mem_gen_0_1.xci" new file mode 100755 index 0000000..aeed882 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_dist_mem_gen_0_1/bd_main_dist_mem_gen_0_1.xci" @@ -0,0 +1,102 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_main_dist_mem_gen_0_1 + + + 9 + 0 + 512 + ./ + zynq + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + no_coe_file_loaded + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 32 + bd_main_dist_mem_gen_0_1 + 0 + ce_overrides_sync_controls + no_coe_file_loaded + false + false + 32 + 0 + 16 + 512 + non_registered + false + false + non_registered + single_port_ram + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynq + + + xc7z010 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 13 + TRUE + . + + ../../ipshared + 2019.1 + OUT_OF_CONTEXT + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_gpio_0_0.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_gpio_0_0.v" new file mode 100755 index 0000000..547e727 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_gpio_0_0.v" @@ -0,0 +1,92 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:gpio:1.0 +// IP Revision: 1 + +(* X_CORE_INFO = "gpio,Vivado 2019.1" *) +(* CHECK_LICENSE_TYPE = "bd_main_gpio_0_0,gpio,{}" *) +(* CORE_GENERATION_INFO = "bd_main_gpio_0_0,gpio,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=gpio,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *) +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module bd_main_gpio_0_0 ( + clk, + rst, + a, + d, + we, + spo, + btn, + led +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN bd_main_sysclk, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) +input wire clk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *) +input wire rst; +input wire [1 : 0] a; +input wire [31 : 0] d; +input wire we; +output wire [31 : 0] spo; +input wire [1 : 0] btn; +output wire [1 : 0] led; + + gpio inst ( + .clk(clk), + .rst(rst), + .a(a), + .d(d), + .we(we), + .spo(spo), + .btn(btn), + .led(led) + ); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_mmapper_0_0.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_mmapper_0_0.v" new file mode 100755 index 0000000..25e6a71 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_mmapper_0_0.v" @@ -0,0 +1,124 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:mmapper:1.0 +// IP Revision: 1 + +(* X_CORE_INFO = "mmapper,Vivado 2019.1" *) +(* CHECK_LICENSE_TYPE = "bd_main_mmapper_0_0,mmapper,{}" *) +(* CORE_GENERATION_INFO = "bd_main_mmapper_0_0,mmapper,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mmapper,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *) +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module bd_main_mmapper_0_0 ( + a, + d, + we, + spo, + bootm_a, + bootm_d, + bootm_we, + bootm_spo, + mainm_a, + mainm_d, + mainm_we, + mainm_spo, + gpio_a, + gpio_d, + gpio_we, + gpio_spo, + uart_a, + uart_d, + uart_we, + uart_spo +); + +input wire [31 : 0] a; +input wire [31 : 0] d; +input wire we; +output wire [31 : 0] spo; +output wire [8 : 0] bootm_a; +output wire [31 : 0] bootm_d; +output wire bootm_we; +input wire [31 : 0] bootm_spo; +output wire [8 : 0] mainm_a; +output wire [31 : 0] mainm_d; +output wire mainm_we; +input wire [31 : 0] mainm_spo; +output wire [1 : 0] gpio_a; +output wire [31 : 0] gpio_d; +output wire gpio_we; +input wire [31 : 0] gpio_spo; +output wire [2 : 0] uart_a; +output wire [31 : 0] uart_d; +output wire uart_we; +input wire [31 : 0] uart_spo; + + mmapper inst ( + .a(a), + .d(d), + .we(we), + .spo(spo), + .bootm_a(bootm_a), + .bootm_d(bootm_d), + .bootm_we(bootm_we), + .bootm_spo(bootm_spo), + .mainm_a(mainm_a), + .mainm_d(mainm_d), + .mainm_we(mainm_we), + .mainm_spo(mainm_spo), + .gpio_a(gpio_a), + .gpio_d(gpio_d), + .gpio_we(gpio_we), + .gpio_spo(gpio_spo), + .uart_a(uart_a), + .uart_d(uart_d), + .uart_we(uart_we), + .uart_spo(uart_spo) + ); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_ooc.xdc" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_ooc.xdc" new file mode 100755 index 0000000..d300e73 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_ooc.xdc" @@ -0,0 +1,11 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ +create_clock -name sysclk -period 8 [get_ports sysclk] + +################################################################################ \ No newline at end of file diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_uart_0_0.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_uart_0_0.v" new file mode 100755 index 0000000..b09a339 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_uart_0_0.v" @@ -0,0 +1,92 @@ +// (c) Copyright 1995-2020 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:uart:1.0 +// IP Revision: 1 + +(* X_CORE_INFO = "uart,Vivado 2019.1" *) +(* CHECK_LICENSE_TYPE = "bd_main_uart_0_0,uart,{}" *) +(* CORE_GENERATION_INFO = "bd_main_uart_0_0,uart,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=uart,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *) +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module bd_main_uart_0_0 ( + clk, + rst, + a, + d, + we, + spo, + rx, + tx +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN bd_main_sysclk, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) +input wire clk; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *) +input wire rst; +input wire [2 : 0] a; +input wire [31 : 0] d; +input wire we; +output wire [31 : 0] spo; +input wire rx; +output wire tx; + + uart inst ( + .clk(clk), + .rst(rst), + .a(a), + .d(d), + .we(we), + .spo(spo), + .rx(rx), + .tx(tx) + ); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_xlslice_0_0/bd_main_xlslice_0_0.xci" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_xlslice_0_0/bd_main_xlslice_0_0.xci" new file mode 100755 index 0000000..db9564e --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/bd_main_xlslice_0_0/bd_main_xlslice_0_0.xci" @@ -0,0 +1,53 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bd_main_xlslice_0_0 + + + 1 + 1 + 2 + bd_main_xlslice_0_0 + 1 + 1 + 2 + 1 + zynq + + + xc7z010 + clg400 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Integrator + 2 + TRUE + . + + ../../ipshared + 2019.1 + GLOBAL + + + + + + + + + + + + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/clock_div_pulse.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/clock_div_pulse.v" new file mode 100755 index 0000000..eccc27f --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/clock_div_pulse.v" @@ -0,0 +1,44 @@ +`timescale 1ns / 1ps +// copied & modified from https://github.com/jamieiles/uart, GPLv2 + +/* + * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud + * rx/tx pair where the rx clcken oversamples by 16x. + */ +module baud_rate_gen + ( + input wire clk, + input rst, + output wire rxclk_en, + output wire txclk_en + ); + + parameter RX_ACC_MAX = 125000000 / (115200 * 16); + parameter TX_ACC_MAX = 125000000 / 115200; + parameter RX_ACC_WIDTH = 20; + parameter TX_ACC_WIDTH = 20; + //parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX); + //parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX); + reg [RX_ACC_WIDTH - 1:0] rx_acc = 0; + reg [TX_ACC_WIDTH - 1:0] tx_acc = 0; + + assign rxclk_en = (rx_acc == 0); + assign txclk_en = (tx_acc == 0); + + always @(posedge clk) begin + if (rst) rx_acc <= 1; + else if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH - 1:0]) + rx_acc <= 0; + else + rx_acc <= rx_acc + 1; + end + + always @(posedge clk) begin + if (rst) tx_acc <= 1; + else if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH - 1:0]) + tx_acc <= 0; + else + tx_acc <= tx_acc + 1; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/cpu-multi-cycle.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/cpu-multi-cycle.v" new file mode 100755 index 0000000..36fb0e5 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/cpu-multi-cycle.v" @@ -0,0 +1,155 @@ +`timescale 1ns / 1ps + +module cpu_multi_cycle + ( + input clk, + input rst, + + output reg [31:0]a, + output reg [31:0]d, + output reg we, + input [31:0]spo + ); + + // internal registers + reg [31:0]instruction = 0; + reg [31:0]pc = 0; + reg [31:0]mdr = 0; + reg [31:0]ALUOut = 0; + reg [31:0]A = 0; + reg [31:0]B = 0; + + // some signals + wire ALUZero; + reg [31:0]newpc; + wire [31:0]imm = {{16{instruction[15]}}, instruction[15:0]}; + + // control unit signals + wire PCWrite; + wire IorD; + wire MemRead; + wire MemWrite; + wire [2:0]RegSrc; + wire IRWrite; + wire [2:0]PCSource; + wire [2:0]ALUm; + wire ALUSrcA; + wire [1:0]ALUSrcB; + wire RegWrite; + wire [1:0]RegDst; + control_unit control_unit_inst + ( + .clk(clk), + .rst(rst), + .instruction(instruction), + .ALUZero(ALUZero), + + .PCWrite(PCWrite), + .IorD(IorD), + .MemRead(MemRead), + .MemWrite(MemWrite), + .RegSrc(RegSrc), + .IRWrite(IRWrite), + .PCSource(PCSource), + .ALUm(ALUm), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .RegWrite(RegWrite), + .RegDst(RegDst) + ); + + // register file + reg [4:0]WriteRegister; + reg [31:0]WriteData; + wire [31:0]ReadData1; + wire [31:0]ReadData2; + register_file register_file_inst + ( + .clk(clk), + .ra0(instruction[25:21]), + .ra1(instruction[20:16]), + .wa(WriteRegister), + .we(RegWrite), + .wd(WriteData), + .rd0(ReadData1), + .rd1(ReadData2) + ); + + // memory mapper + reg [31:0]mem_addr; + reg [31:0]MemData; + always @ (*) begin + a = mem_addr; + d = B; + we = MemWrite; + MemData = spo; + end + + // ALU + reg [31:0]ALUIn1; + reg [31:0]ALUIn2; + wire [31:0]ALUResult; + alu alu_inst + ( + .m(ALUm), + .a(ALUIn1), + .b(ALUIn2), + .y(ALUResult), + .zf(ALUZero) + //.cf(), + //.of() + ); + + // datapath -- main + always @ (*) begin + case (IorD) + 0: mem_addr = pc; + 1: mem_addr = ALUOut; + endcase + case (RegDst) + 0: WriteRegister = instruction[20:16]; + 1: WriteRegister = instruction[15:11]; + 2: WriteRegister = 5'b11111; + endcase + case (RegSrc) + 0: WriteData = ALUOut; + 1: WriteData = mdr; + 2: WriteData = {instruction[15:0], 16'b0}; + 3: WriteData = pc; + endcase + case (ALUSrcB) + 0: ALUIn2 = B; + 1: ALUIn2 = 4; + 2: ALUIn2 = imm; + 3: ALUIn2 = imm << 2; + endcase + case (ALUSrcA) + 0: ALUIn1 = pc; + 1: ALUIn1 = A; + endcase + case (PCSource) + 0: newpc = ALUResult; + 1: newpc = ALUOut; + 2: newpc = {pc[31:28], instruction[25:0], 2'b0}; + 3: newpc = A; + endcase + end + always @ (posedge clk) begin + if (rst) begin + pc <= 32'b0; + instruction <= 0; + mdr <= 0; + ALUOut <= 0; + A <= 0; + B <= 0; + end + else begin + A <= ReadData1; + B <= ReadData2; + ALUOut <= ALUResult; + mdr <= MemData; + if (PCWrite) pc <= newpc; + if (IRWrite) instruction <= MemData; + end + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/cpu_control_unit.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/cpu_control_unit.v" new file mode 100755 index 0000000..117851b --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/cpu_control_unit.v" @@ -0,0 +1,202 @@ +`timescale 1ns / 1ps + +module control_unit + ( + input clk, + input rst, + input [31:0]instruction, + input ALUZero, + + output reg PCWrite, + output reg IorD, + output reg MemRead, + output reg MemWrite, + output reg [2:0]RegSrc, + output reg IRWrite, + output reg [2:0]PCSource, + output reg [2:0]ALUm, + output reg ALUSrcA, + output reg [1:0]ALUSrcB, + output reg RegWrite, + output reg [1:0]RegDst + ); + + // control unit FSM state names + reg [7:0]phase = IF; + localparam IF = 0; + localparam ID_RF = 1; + localparam MEM_ADDR_CALC = 2; + localparam MEM_ACCESS_LW = 3; + localparam WB = 4; + localparam MEM_ACCESS_SW = 5; + localparam ADDI_END = 12; + localparam R_EX = 6; + localparam R_END = 7; + localparam BEQ_END = 8; + localparam J_END = 9; + localparam JAL_END = 10; + localparam JR_END = 11; + localparam LUI_END = 13; + localparam I_MFC0_END = 14; + //localparam I_MTC0_END = 15; + localparam I_ERET_END = 16; + localparam I_SYSCALL_END = 17; + localparam I_INT_END = 18; + localparam BAD = 99; + + // instruction[31:26] instruction type + wire [5:0]instr_type = instruction[31:26]; + localparam TYPE_REG = 6'b000000; + localparam TYPE_ADDI = 6'b001000; + localparam TYPE_LUI = 6'b001111; + localparam TYPE_LW = 6'b100011; + localparam TYPE_SW = 6'b101011; + localparam TYPE_BEQ = 6'b000100; + localparam TYPE_J = 6'b000010; + localparam TYPE_JAL = 6'b000011; + localparam TYPE_BAD = 0; + + // instruction[5:0] function + wire [5:0]instr_funct = instruction[5:0]; + localparam FUNCT_ADD = 6'b100000; + localparam FUNCT_SUB = 6'b100010; + localparam FUNCT_AND = 6'b100100; + localparam FUNCT_OR = 6'b100101; + localparam FUNCT_SLT = 6'b101010; + localparam FUNCT_JR = 6'b001000; + + // instruction label + reg [31:0]Op; + localparam OP_ADD = 91001; + localparam OP_SUB = 91001; + localparam OP_AND = 91001; + localparam OP_OR = 91001; + localparam OP_SLT = 91001; + localparam OP_ADDI = 90002; + localparam OP_LUI = 90003; + localparam OP_LW = 90004; + localparam OP_SW = 90005; + localparam OP_BEQ = 90006; + localparam OP_J = 90007; + localparam OP_JAL = 90008; + localparam OP_JR = 90009; + localparam OP_NOP = 91000; + localparam OP_BAD = 99000; + + // instruction decoding + always @ (*) begin + Op = OP_BAD; + case (instr_type) + TYPE_REG: case (instr_funct) + FUNCT_ADD: Op = OP_ADD; + FUNCT_SUB: Op = OP_SUB; + FUNCT_AND: Op = OP_AND; + FUNCT_OR: Op = OP_OR; + FUNCT_SLT: Op = OP_SLT; + FUNCT_JR: Op = OP_JR; + default: ; + endcase + TYPE_ADDI: Op = OP_ADDI; + TYPE_LUI: Op = OP_LUI; + TYPE_LW: Op = OP_LW; + TYPE_SW: Op = OP_SW; + TYPE_BEQ: Op = OP_BEQ; + TYPE_J: Op = OP_J; + TYPE_JAL: Op = OP_JAL; + default: ; + endcase + if (instruction == 32'b0) Op = OP_NOP; + end + + // control fsm + always @ (posedge clk) begin + if (rst) begin + phase <= IF; + end + else begin + case(phase) + IF: phase <= ID_RF; + ID_RF: begin + case(Op) + OP_NOP: phase <= IF; + + OP_LW: phase <= MEM_ADDR_CALC; + OP_SW: phase <= MEM_ADDR_CALC; + OP_ADDI: phase <= MEM_ADDR_CALC; + OP_LUI: phase <= LUI_END; + + OP_ADD: phase <= R_EX; + OP_SUB: phase <= R_EX; + OP_AND: phase <= R_EX; + OP_OR: phase <= R_EX; + + OP_BEQ: phase <= BEQ_END; + + OP_J: phase <= J_END; + OP_JAL: phase <= JAL_END; + OP_JR: phase <= JR_END; + default: phase <= BAD; + endcase + end + MEM_ADDR_CALC: case (Op) + OP_LW: phase <= MEM_ACCESS_LW; + OP_SW: phase <= MEM_ACCESS_SW; + OP_ADDI: phase <= ADDI_END; + default: phase <= BAD; + endcase + MEM_ACCESS_LW: phase <= WB; + WB: phase <= IF; + MEM_ACCESS_SW: phase <= IF; + ADDI_END: phase <= IF; + LUI_END: phase <= IF; + R_EX: phase <= R_END; + R_END: phase <= IF; + BEQ_END: phase <= IF; + J_END: phase <= IF; + JAL_END: phase <= IF; + JR_END: phase <= IF; + default: phase <= BAD; + endcase + end + end + + // control signals for each FSM states + always @ (*) begin + PCWrite = 0; + IorD = 0; + MemRead = 0; + MemWrite = 0; + RegSrc = 3'b000; + IRWrite = 0; + PCSource = 3'b000; + ALUm = 3'b000; + ALUSrcA = 0; + ALUSrcB = 0; + RegWrite = 0; + RegDst = 2'b00; + case (phase) + IF: begin MemRead = 1; ALUSrcB = 2'b01; IRWrite = 1; PCWrite = 1; end + ID_RF: ALUSrcB = 2'b11; + MEM_ADDR_CALC: begin ALUSrcA = 1; ALUSrcB = 2'b10; end + MEM_ACCESS_LW: begin MemRead = 1; IorD = 1; end + ADDI_END: begin RegWrite = 1; end + LUI_END: begin RegWrite = 1; RegSrc = 3'b010; end + WB: begin RegWrite = 1; RegSrc = 3'b001; end + MEM_ACCESS_SW: begin IorD = 1; MemWrite = 1; end + R_EX: begin + ALUSrcA = 1; + case (Op) + OP_ADD: ALUm = 3'b000; + OP_SUB: ALUm = 3'b001; + OP_AND: ALUm = 3'b010; + OP_OR: ALUm = 3'b011; + endcase + end + R_END: begin RegWrite = 1; RegDst = 2'b01; end + BEQ_END: begin ALUSrcA = 1; ALUm = 3'b001; PCWrite = ALUZero; PCSource = 3'b001; end + J_END: begin PCWrite = 1; PCSource = 3'b010; end + JAL_END: begin PCWrite = 1; PCSource = 3'b010; RegWrite = 1; RegDst = 2'b10; RegSrc = 3'b011; end + JR_END: begin PCWrite = 1; PCSource = 3'b011; end + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/debounce.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/debounce.v" new file mode 100755 index 0000000..8c91b2d --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/debounce.v" @@ -0,0 +1,77 @@ +`timescale 1ns / 1ps +// input button debounce +// https://timetoexplore.net/blog/arty-fpga-verilog-03 + +module debounce + #(parameter N = 2) + ( + input clk, + input [N-1:0]i_btn, + output reg [N-1:0]o_state = 0 + //output o_ondn, + //output o_onup + ); + + // sync with clock and combat metastability + reg [N-1:0]sync_0 = 0; + reg [N-1:0]sync_1 = 0; + always @(posedge clk) sync_0 <= i_btn; + always @(posedge clk) sync_1 <= sync_0; + + // 2.6 ms counter at 100 MHz + reg [18:0] counter; + wire idle = (o_state == sync_1); + wire [18:0]max = 10; + + always @(posedge clk) + begin + if (idle) + counter <= 0; + else + begin + counter <= counter + 1; + if (counter == max) + o_state <= sync_1; + end + end + + //assign o_ondn = ~idle & max & ~o_state; + //assign o_onup = ~idle & max & o_state; +endmodule +//module debounce + //#(parameter N = 4) + //( + //input clk, + //input [N-1:0]i_btn, + //output reg [N-1:0]o_state = 0 + ////output o_ondn, + ////output o_onup + //); + + //// sync with clock and combat metastability + //reg [N-1:0]sync_0 = 0; + //reg [N-1:0]sync_1 = 0; + //always @(posedge clk) sync_0 <= i_btn; + //always @(posedge clk) sync_1 <= sync_0; + + //// 2.6 ms(*2) counter at 100 MHz + //reg [18:0] counter = 0; + ////reg [19:0] counter; + //wire idle = (o_state == sync_1); + + //always @(posedge clk) + //begin + //if (idle) + //counter <= 0; + //else + //begin + //counter <= counter + 1; + //if (counter == 19'b11111) + ////o_state <= ~o_state; + //o_state <= sync_1; + //end + //end + + ////assign o_ondn = ~idle & max & ~o_state; + ////assign o_onup = ~idle & max & o_state; +//endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/gpio.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/gpio.v" new file mode 100755 index 0000000..a818097 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/gpio.v" @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps + +module gpio + ( + input clk, + input rst, + input [1:0]a, + input [31:0]d, + input we, + output reg [31:0]spo, + + input [1:0]btn, + output reg [1:0]led + ); + + always @ (*) begin + case (a) + 0: spo = {31'b0, btn[0]}; + 1: spo = {31'b0, btn[1]}; + 2: spo = {31'b0, led[0]}; + 3: spo = {31'b0, led[1]}; + default: spo = 32'b0; + endcase + end + + always @ (posedge clk) begin + if (rst) begin + led <= 2'b11; + end + else if (we) begin + case (a) + 2: led[0] <= d[0]; + 3: led[1] <= d[0]; + default: ; + endcase + end + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/mmapper.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/mmapper.v" new file mode 100755 index 0000000..dd4205c --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/mmapper.v" @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps + +module mmapper + ( + input [31:0]a, + input [31:0]d, + //input [31:0]dpra, + input we, + output reg [31:0]spo, + //output reg [31:0]dpo = 0, + + // 1024*32(4KB) boot rom: 0x00000000 + output reg [8:0]bootm_a, + output reg [31:0]bootm_d, + output reg bootm_we, + input [31:0]bootm_spo, + + // main memory: 0x10000000 + output reg [8:0]mainm_a, + output reg [31:0]mainm_d, + output reg mainm_we, + input [31:0]mainm_spo, + + // gpio: 0x20000000 + output reg [1:0]gpio_a, + output reg [31:0]gpio_d, + output reg gpio_we, + input [31:0]gpio_spo, + + // fifo uart: + // write 0x30000000 + // full 0x30000004 + // empty 0x30000008 + output reg [2:0]uart_a, + output reg [31:0]uart_d, + output reg uart_we, + input [31:0]uart_spo + ); + + always @ (*) begin + bootm_a = a[10:2]; + bootm_d = d; + mainm_a = a[10:2]; + mainm_d = d; + gpio_a = a[3:2]; + gpio_d = d; + uart_a = a[4:2]; + uart_d = d; + end + + always @ (*) begin + bootm_we = 0; + mainm_we = 0; + gpio_we = 0; + uart_we = 0; + case (a[31:28]) + 0: begin spo = bootm_spo; bootm_we = we; end + 1: begin spo = mainm_spo; mainm_we = we; end + 2: begin spo = gpio_spo; gpio_we = we; end + 3: begin spo = uart_spo; uart_we = we; end + default: ; + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/register_file.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/register_file.v" new file mode 100755 index 0000000..ca528a7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/register_file.v" @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps +// pCPU regfile with debug port + +module register_file + #(parameter WIDTH = 32) + ( + input clk, + input [4:0]ra0, + input [4:0]ra1, + input [4:0]ra2, + input [4:0]wa, + input we, + input [WIDTH-1:0]wd, + output reg [WIDTH-1:0]rd0, + output reg [WIDTH-1:0]rd1, + output reg [WIDTH-1:0]rd2 + ); + + reg [WIDTH-1:0]regfile[31:0]; + initial $readmemh("/home/petergu/MyHome/pComputer/pCPU/regfile.dat", regfile); + + always @ (*) begin + if (ra0 == 5'b0) rd0 = 0; + else rd0 = regfile[ra0]; + if (ra1 == 5'b0) rd1 = 0; + else rd1 = regfile[ra1]; + if (ra2 == 5'b0) rd2 = 0; + else rd2 = regfile[ra2]; + end + + always @ (posedge clk) begin + if (we) begin + if (wa != 5'b0) begin + regfile[wa] <= wd; + end + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/result_echo.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/result_echo.coe" new file mode 100755 index 0000000..6905a11 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/result_echo.coe" @@ -0,0 +1,106 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +20040000 +0c000050 +00000000 +2004004f +0c000034 +00000000 +2004004b +0c000034 +00000000 +3c100000 +8e100180 +00000000 +2004000d +0c000034 +00000000 +2004000a +0c000034 +00000000 +20110000 +0c000042 +00000000 +02114020 +ad020000 +2008000d +10480007 +00000000 +2004002e +0c000034 +00000000 +22310004 +08000013 +00000000 +2004000d +0c000034 +00000000 +2004000a +0c000034 +00000000 +20110000 +02114020 +8d040000 +00000000 +0c000034 +00000000 +2008000d +1088ffde +00000000 +22310004 +08000027 +00000000 +00000000 +00000000 +3c0a0000 +8d4a0190 +00000000 +8d480008 +00000000 +1100fffd +00000000 +ad440000 +8d480008 +00000000 +1100fffd +00000000 +03e00008 +00000000 +3c0a0000 +8d4a0190 +00000000 +20090001 +ad490004 +8d480004 +00000000 +1100fffd +00000000 +8d480000 +00000000 +21020000 +03e00008 +00000000 +3c0a0000 +8d4a0194 +00000000 +21490018 +ad240000 +2149001c +ad240000 +21490020 +ad240000 +21490024 +ad240000 +03e00008 +00000000 +00000000 +00000000 +00000000 +10000000 +00000000 +00000000 +00000000 +30000000 +20000000 +00000000 +00000000 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/uart.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/uart.v" new file mode 100755 index 0000000..887d687 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/src/uart.v" @@ -0,0 +1,175 @@ +`timescale 1ns / 1ps +// pComputer UART I/O +// input XXMHz, 16x oversampling +// warning: not very reliable: read/write together case, ... +// so need special software care(better to write one value and wait until idle) +// +// write 0x00: transmit data +// read 0x00: received data +// write 0x01: begin receiving +// read 0x01: receive done? +// read 0x02: transmit done? +// *need to x4 these addresses in assembly! + +module uart + ( + input clk, + input rst, + + input [2:0]a, + input [31:0]d, + input we, + output reg [31:0]spo, + + //output wire read_enabled_out, + //output wire rx_state_out0, + //output wire rx_state_out1, + + input rx, + output reg tx = 1 + ); + + wire rxclk_en; + wire txclk_en; + baud_rate_gen baud_rate_gen_inst + ( + .clk(clk), + .rst(rst), + .rxclk_en(rxclk_en), + .txclk_en(txclk_en) + ); + + localparam IDLE = 3'b000; + //localparam PREPARE1 = 3'b001; + //localparam PREPARE2 = 3'b010; + localparam START = 3'b011; + localparam DATA = 3'b100; + localparam STOP = 3'b101; + reg [2:0]state_tx = IDLE; + reg [7:0]data_tx = 8'h00; + reg [2:0]bitpos_tx = 0; + + localparam RX_STATE_START = 2'b01; + localparam RX_STATE_DATA = 2'b10; + localparam RX_STATE_STOP = 2'b11; + reg [1:0]state_rx = RX_STATE_START; + //assign rx_state_out0 = state_rx[0]; + //assign rx_state_out1 = state_rx[1]; + reg [3:0]sample = 0; + reg [3:0]bitpos_rx = 0; + reg [7:0]scratch = 8'b0; + + reg read_enabled = 0; + reg [7:0]data_rx = 0; + //reg [7:0]data_rx_ready = 0; + + always @ (*) begin + if (a == 3'b000) spo = {24'b0, data_rx}; + else if (a == 3'b001) spo = {31'b0, !read_enabled}; + else if (a == 3'b010) spo = {31'b0, (state_tx == IDLE)}; + else spo = 32'b0; + end + always @ (posedge clk) begin + if (rst) begin + tx <= 1'b1; + data_tx <= 0; + bitpos_tx <= 0; + state_tx <= IDLE; + + data_rx <= 0; + read_enabled <= 0; + //data_rx_ready <= 0; + state_rx <= RX_STATE_START; + sample <= 0; + end + else begin + //if (we) begin + //if (a == 3'b011 & d[0]) begin + //// so no way to set this to 0(cancel reading)! + //read_enabled <= 1; + //end + //if (a == 3'b000 & !fifo_full) begin + //if (a == 3'b000 & !tx_write) begin + ////fifo_enqueue <= 1; + ////fifo_in <= d[7:0]; + //data_tx <= d[7:0]; + //end + //else begin + //fifo_enqueue <= 0; + //fifo_in <= 8'b0; + //end + //end + case (state_tx) + IDLE: if (we & (a == 3'b000)) begin + data_tx <= d[7:0]; + state_tx <= START; + end + START: if (txclk_en) begin + bitpos_tx <= 0; + tx <= 1'b0; + state_tx <= DATA; + end + DATA: if (txclk_en) begin + if (bitpos_tx == 7) state_tx <= STOP; + else bitpos_tx <= bitpos_tx + 1; + tx <= data_tx[bitpos_tx]; + end + STOP: if (txclk_en) begin + tx <= 1'b1; + state_tx <= IDLE; + end + default: ; + endcase + + if (we & a == 3'b001) begin + read_enabled <= 1; + end + else if (rxclk_en) begin + case (state_rx) + /* + Start counting from the first low sample, once we've + sampled a full bit, start collecting data bits. + */ + RX_STATE_START: begin + //data_rx_ready <= 0; + if (!rx || sample != 0) sample <= sample + 1; + if (sample == 15) begin + state_rx <= RX_STATE_DATA; + bitpos_rx <= 0; + sample <= 0; + scratch <= 0; + end + end + RX_STATE_DATA: begin + sample <= sample + 1; + if (sample == 8) begin + scratch[bitpos_rx[2:0]] <= rx; + bitpos_rx <= bitpos_rx + 1; + end + if (bitpos_rx == 8 && sample == 15) state_rx <= RX_STATE_STOP; + end + /* + Our baud clock may not be running at exactly the + same rate as the transmitter. If we thing that + we're at least half way into the stop bit, allow + transition into handling the next start bit. + */ + RX_STATE_STOP: begin + if (sample == 15 || (sample >= 8 && !rx)) begin + state_rx <= RX_STATE_START; + data_rx <= scratch; + //data_rx_ready <= 1; + read_enabled <= 0; + sample <= 0; + end else begin + sample <= sample + 1; + end + end + default: state_rx <= RX_STATE_START; + endcase + end + + + end + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/xgui/bd_main_v1_0.tcl" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/xgui/bd_main_v1_0.tcl" new file mode 100644 index 0000000..0db18e9 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/ip/xgui/bd_main_v1_0.tcl" @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/constrs_1/imports/lab6/ebaz4205.xdc" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/constrs_1/imports/lab6/ebaz4205.xdc" new file mode 100644 index 0000000..745b2b7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/constrs_1/imports/lab6/ebaz4205.xdc" @@ -0,0 +1,56 @@ +#set_property IOSTANDARD LVCMOS33 [get_ports led_g] +#set_property IOSTANDARD LVCMOS33 [get_ports led_r] +set_property IOSTANDARD LVCMOS33 [get_ports {leddata[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {leddata[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports uart_rx] +set_property IOSTANDARD LVCMOS33 [get_ports uart_tx] +set_property IOSTANDARD LVCMOS33 [get_ports {btndata[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {btndata[1]}] + +#set_property PACKAGE_PIN W13 [get_ports led_g] +#set_property PACKAGE_PIN W14 [get_ports led_r] +# G20 J18 for 5 6 +# DATA2-15 +set_property PACKAGE_PIN L16 [get_ports {leddata[0]}] +# DATA2-16 +set_property PACKAGE_PIN L19 [get_ports {leddata[1]}] +# DATA2-17 +set_property PACKAGE_PIN M18 [get_ports uart_rx] +# DATA2-18 +set_property PACKAGE_PIN L20 [get_ports uart_tx] +# DATA2-19 +set_property PACKAGE_PIN M20 [get_ports {btndata[0]}] +# DATA2-20 +set_property PACKAGE_PIN L17 [get_ports {btndata[1]}] + +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_GMII_RX_CLK_0] +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_GMII_TX_CLK_0] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_rxd[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {ENET0_GMII_TX_EN_0[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {enet0_gmii_txd[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports ENET0_GMII_RX_DV_0] + +set_property IOSTANDARD LVCMOS33 [get_ports MDIO_ETHERNET_0_0_mdc] +set_property IOSTANDARD LVCMOS33 [get_ports MDIO_ETHERNET_0_0_mdio_io] + +set_property PACKAGE_PIN U14 [get_ports ENET0_GMII_RX_CLK_0] +set_property PACKAGE_PIN U15 [get_ports ENET0_GMII_TX_CLK_0] +set_property PACKAGE_PIN Y17 [get_ports {enet0_gmii_rxd[3]}] +set_property PACKAGE_PIN V17 [get_ports {enet0_gmii_rxd[2]}] +set_property PACKAGE_PIN V16 [get_ports {enet0_gmii_rxd[1]}] +set_property PACKAGE_PIN Y16 [get_ports {enet0_gmii_rxd[0]}] +set_property PACKAGE_PIN W19 [get_ports {ENET0_GMII_TX_EN_0[0]}] +set_property PACKAGE_PIN W16 [get_ports ENET0_GMII_RX_DV_0] +set_property PACKAGE_PIN Y19 [get_ports {enet0_gmii_txd[3]}] +set_property PACKAGE_PIN V18 [get_ports {enet0_gmii_txd[2]}] +set_property PACKAGE_PIN Y18 [get_ports {enet0_gmii_txd[1]}] +set_property PACKAGE_PIN W18 [get_ports {enet0_gmii_txd[0]}] + +set_property PACKAGE_PIN W15 [get_ports MDIO_ETHERNET_0_0_mdc] +set_property PACKAGE_PIN Y14 [get_ports MDIO_ETHERNET_0_0_mdio_io] diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sim_1/new/bd_main_simu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sim_1/new/bd_main_simu.v" new file mode 100644 index 0000000..e29b86f --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sim_1/new/bd_main_simu.v" @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps + +module top_simu(); + reg clk = 0; + reg [1:0]btn = 0; + wire [1:0]led; + + bd_main_wrapper bd_main_wrapper_inst + ( + .sysclk(clk), + .btndata(btn), + .leddata(led) + ); + + initial begin + clk = 0; + forever #5 clk = ~clk; + end + + initial begin + btn = 2'b11; + #200 + btn = 2'b00; + //#10 + //btn = 4'b0000; + + //#1000 + //btn = 4'b0010; + + #3000 + $finish; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/hdl/bd_hello_wrapper.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/hdl/bd_hello_wrapper.v" new file mode 100644 index 0000000..8e598c6 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/hdl/bd_hello_wrapper.v" @@ -0,0 +1,158 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019 +//Date : Fri Jul 10 16:28:18 2020 +//Host : petergu-dell running 64-bit Arch Linux +//Command : generate_target bd_hello_wrapper.bd +//Design : bd_hello_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_hello_wrapper + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + ENET0_GMII_RX_CLK_0, + ENET0_GMII_RX_DV_0, + ENET0_GMII_TX_CLK_0, + ENET0_GMII_TX_EN_0, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + MDIO_ETHERNET_0_0_mdc, + MDIO_ETHERNET_0_0_mdio_io, + btndata, + enet0_gmii_rxd, + enet0_gmii_txd, + leddata, + uart_rx, + uart_tx); + inout [14:0]DDR_addr; + inout [2:0]DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [3:0]DDR_dm; + inout [31:0]DDR_dq; + inout [3:0]DDR_dqs_n; + inout [3:0]DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + input ENET0_GMII_RX_CLK_0; + input ENET0_GMII_RX_DV_0; + input ENET0_GMII_TX_CLK_0; + output [0:0]ENET0_GMII_TX_EN_0; + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0]FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + output MDIO_ETHERNET_0_0_mdc; + inout MDIO_ETHERNET_0_0_mdio_io; + input [1:0]btndata; + input [3:0]enet0_gmii_rxd; + output [3:0]enet0_gmii_txd; + output [1:0]leddata; + input uart_rx; + output uart_tx; + + wire [14:0]DDR_addr; + wire [2:0]DDR_ba; + wire DDR_cas_n; + wire DDR_ck_n; + wire DDR_ck_p; + wire DDR_cke; + wire DDR_cs_n; + wire [3:0]DDR_dm; + wire [31:0]DDR_dq; + wire [3:0]DDR_dqs_n; + wire [3:0]DDR_dqs_p; + wire DDR_odt; + wire DDR_ras_n; + wire DDR_reset_n; + wire DDR_we_n; + wire ENET0_GMII_RX_CLK_0; + wire ENET0_GMII_RX_DV_0; + wire ENET0_GMII_TX_CLK_0; + wire [0:0]ENET0_GMII_TX_EN_0; + wire FIXED_IO_ddr_vrn; + wire FIXED_IO_ddr_vrp; + wire [53:0]FIXED_IO_mio; + wire FIXED_IO_ps_clk; + wire FIXED_IO_ps_porb; + wire FIXED_IO_ps_srstb; + wire MDIO_ETHERNET_0_0_mdc; + wire MDIO_ETHERNET_0_0_mdio_i; + wire MDIO_ETHERNET_0_0_mdio_io; + wire MDIO_ETHERNET_0_0_mdio_o; + wire MDIO_ETHERNET_0_0_mdio_t; + wire [1:0]btndata; + wire [3:0]enet0_gmii_rxd; + wire [3:0]enet0_gmii_txd; + wire [1:0]leddata; + wire uart_rx; + wire uart_tx; + + IOBUF MDIO_ETHERNET_0_0_mdio_iobuf + (.I(MDIO_ETHERNET_0_0_mdio_o), + .IO(MDIO_ETHERNET_0_0_mdio_io), + .O(MDIO_ETHERNET_0_0_mdio_i), + .T(MDIO_ETHERNET_0_0_mdio_t)); + bd_hello bd_hello_i + (.DDR_addr(DDR_addr), + .DDR_ba(DDR_ba), + .DDR_cas_n(DDR_cas_n), + .DDR_ck_n(DDR_ck_n), + .DDR_ck_p(DDR_ck_p), + .DDR_cke(DDR_cke), + .DDR_cs_n(DDR_cs_n), + .DDR_dm(DDR_dm), + .DDR_dq(DDR_dq), + .DDR_dqs_n(DDR_dqs_n), + .DDR_dqs_p(DDR_dqs_p), + .DDR_odt(DDR_odt), + .DDR_ras_n(DDR_ras_n), + .DDR_reset_n(DDR_reset_n), + .DDR_we_n(DDR_we_n), + .ENET0_GMII_RX_CLK_0(ENET0_GMII_RX_CLK_0), + .ENET0_GMII_RX_DV_0(ENET0_GMII_RX_DV_0), + .ENET0_GMII_TX_CLK_0(ENET0_GMII_TX_CLK_0), + .ENET0_GMII_TX_EN_0(ENET0_GMII_TX_EN_0), + .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), + .FIXED_IO_mio(FIXED_IO_mio), + .FIXED_IO_ps_clk(FIXED_IO_ps_clk), + .FIXED_IO_ps_porb(FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), + .MDIO_ETHERNET_0_0_mdc(MDIO_ETHERNET_0_0_mdc), + .MDIO_ETHERNET_0_0_mdio_i(MDIO_ETHERNET_0_0_mdio_i), + .MDIO_ETHERNET_0_0_mdio_o(MDIO_ETHERNET_0_0_mdio_o), + .MDIO_ETHERNET_0_0_mdio_t(MDIO_ETHERNET_0_0_mdio_t), + .btndata(btndata), + .enet0_gmii_rxd(enet0_gmii_rxd), + .enet0_gmii_txd(enet0_gmii_txd), + .leddata(leddata), + .uart_rx(uart_rx), + .uart_tx(uart_tx)); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/ip/bd_hello_bd_main_0_2/src/result_echo.coe" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/ip/bd_hello_bd_main_0_2/src/result_echo.coe" new file mode 100755 index 0000000..6905a11 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/ip/bd_hello_bd_main_0_2/src/result_echo.coe" @@ -0,0 +1,106 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +20040000 +0c000050 +00000000 +2004004f +0c000034 +00000000 +2004004b +0c000034 +00000000 +3c100000 +8e100180 +00000000 +2004000d +0c000034 +00000000 +2004000a +0c000034 +00000000 +20110000 +0c000042 +00000000 +02114020 +ad020000 +2008000d +10480007 +00000000 +2004002e +0c000034 +00000000 +22310004 +08000013 +00000000 +2004000d +0c000034 +00000000 +2004000a +0c000034 +00000000 +20110000 +02114020 +8d040000 +00000000 +0c000034 +00000000 +2008000d +1088ffde +00000000 +22310004 +08000027 +00000000 +00000000 +00000000 +3c0a0000 +8d4a0190 +00000000 +8d480008 +00000000 +1100fffd +00000000 +ad440000 +8d480008 +00000000 +1100fffd +00000000 +03e00008 +00000000 +3c0a0000 +8d4a0190 +00000000 +20090001 +ad490004 +8d480004 +00000000 +1100fffd +00000000 +8d480000 +00000000 +21020000 +03e00008 +00000000 +3c0a0000 +8d4a0194 +00000000 +21490018 +ad240000 +2149001c +ad240000 +21490020 +ad240000 +21490024 +ad240000 +03e00008 +00000000 +00000000 +00000000 +00000000 +10000000 +00000000 +00000000 +00000000 +30000000 +20000000 +00000000 +00000000 diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_main/hdl/bd_main_wrapper.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_main/hdl/bd_main_wrapper.v" new file mode 100644 index 0000000..2b83c94 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_main/hdl/bd_main_wrapper.v" @@ -0,0 +1,36 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.1 (lin64) Build 2552052 Fri May 24 14:47:09 MDT 2019 +//Date : Fri Jul 10 16:25:12 2020 +//Host : petergu-dell running 64-bit Arch Linux +//Command : generate_target bd_main_wrapper.bd +//Design : bd_main_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module bd_main_wrapper + (btndata, + leddata, + sysclk, + uart_rx, + uart_tx); + input [1:0]btndata; + output [1:0]leddata; + input sysclk; + input uart_rx; + output uart_tx; + + wire [1:0]btndata; + wire [1:0]leddata; + wire sysclk; + wire uart_rx; + wire uart_tx; + + bd_main bd_main_i + (.btndata(btndata), + .leddata(leddata), + .sysclk(sysclk), + .uart_rx(uart_rx), + .uart_tx(uart_tx)); +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/alu.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/alu.v" new file mode 100644 index 0000000..af53a11 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/alu.v" @@ -0,0 +1,67 @@ +`timescale 1ns / 1ps +// ALU +// 2020 COD Lab1 +// ustcpetergu + +module alu + #(parameter WIDTH = 32) + ( + input [2:0]m, // selection + input [WIDTH-1:0]a, b, // input + output [WIDTH-1:0]y, // result + output zf, // zero flag + output cf, // carry out flag: WIDTH bit + output of // overflow flag: WIDTH-1 sign bit + ); + + reg [WIDTH-1:0]regy; + reg regcf; + reg regof; + reg regzf; + assign y = regy; + assign cf = regcf; + assign of = regof; + assign zf = regzf; + // assign zf = (regy == 0); + + always @ (a, b, m) begin + case(m) + 3'b000: begin // add + {regcf, regy} = a + b; + regof = (!a[WIDTH-1] & !b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b001: begin // sub + {regcf, regy} = a - b; + regof = (!a[WIDTH-1] & b[WIDTH-1] & regy[WIDTH-1]) | + (a[WIDTH-1] & !b[WIDTH-1] & !regy[WIDTH-1]); + regzf = (regy == 0); + end + 3'b010: begin // and + regy = a & b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b011: begin // or + regy = a | b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + 3'b100: begin // xor + regy = a ^ b; + regzf = (regy == 0); + regcf = 0; + regof = 0; + end + default: begin // error + regy = 0; + regzf = 0; + regcf = 0; + regof = 0; + end + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/clock_div_pulse.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/clock_div_pulse.v" new file mode 100644 index 0000000..eccc27f --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/clock_div_pulse.v" @@ -0,0 +1,44 @@ +`timescale 1ns / 1ps +// copied & modified from https://github.com/jamieiles/uart, GPLv2 + +/* + * Hacky baud rate generator to divide a 50MHz clock into a 115200 baud + * rx/tx pair where the rx clcken oversamples by 16x. + */ +module baud_rate_gen + ( + input wire clk, + input rst, + output wire rxclk_en, + output wire txclk_en + ); + + parameter RX_ACC_MAX = 125000000 / (115200 * 16); + parameter TX_ACC_MAX = 125000000 / 115200; + parameter RX_ACC_WIDTH = 20; + parameter TX_ACC_WIDTH = 20; + //parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX); + //parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX); + reg [RX_ACC_WIDTH - 1:0] rx_acc = 0; + reg [TX_ACC_WIDTH - 1:0] tx_acc = 0; + + assign rxclk_en = (rx_acc == 0); + assign txclk_en = (tx_acc == 0); + + always @(posedge clk) begin + if (rst) rx_acc <= 1; + else if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH - 1:0]) + rx_acc <= 0; + else + rx_acc <= rx_acc + 1; + end + + always @(posedge clk) begin + if (rst) tx_acc <= 1; + else if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH - 1:0]) + tx_acc <= 0; + else + tx_acc <= tx_acc + 1; + end + +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu-multi-cycle.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu-multi-cycle.v" new file mode 100644 index 0000000..36fb0e5 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu-multi-cycle.v" @@ -0,0 +1,155 @@ +`timescale 1ns / 1ps + +module cpu_multi_cycle + ( + input clk, + input rst, + + output reg [31:0]a, + output reg [31:0]d, + output reg we, + input [31:0]spo + ); + + // internal registers + reg [31:0]instruction = 0; + reg [31:0]pc = 0; + reg [31:0]mdr = 0; + reg [31:0]ALUOut = 0; + reg [31:0]A = 0; + reg [31:0]B = 0; + + // some signals + wire ALUZero; + reg [31:0]newpc; + wire [31:0]imm = {{16{instruction[15]}}, instruction[15:0]}; + + // control unit signals + wire PCWrite; + wire IorD; + wire MemRead; + wire MemWrite; + wire [2:0]RegSrc; + wire IRWrite; + wire [2:0]PCSource; + wire [2:0]ALUm; + wire ALUSrcA; + wire [1:0]ALUSrcB; + wire RegWrite; + wire [1:0]RegDst; + control_unit control_unit_inst + ( + .clk(clk), + .rst(rst), + .instruction(instruction), + .ALUZero(ALUZero), + + .PCWrite(PCWrite), + .IorD(IorD), + .MemRead(MemRead), + .MemWrite(MemWrite), + .RegSrc(RegSrc), + .IRWrite(IRWrite), + .PCSource(PCSource), + .ALUm(ALUm), + .ALUSrcA(ALUSrcA), + .ALUSrcB(ALUSrcB), + .RegWrite(RegWrite), + .RegDst(RegDst) + ); + + // register file + reg [4:0]WriteRegister; + reg [31:0]WriteData; + wire [31:0]ReadData1; + wire [31:0]ReadData2; + register_file register_file_inst + ( + .clk(clk), + .ra0(instruction[25:21]), + .ra1(instruction[20:16]), + .wa(WriteRegister), + .we(RegWrite), + .wd(WriteData), + .rd0(ReadData1), + .rd1(ReadData2) + ); + + // memory mapper + reg [31:0]mem_addr; + reg [31:0]MemData; + always @ (*) begin + a = mem_addr; + d = B; + we = MemWrite; + MemData = spo; + end + + // ALU + reg [31:0]ALUIn1; + reg [31:0]ALUIn2; + wire [31:0]ALUResult; + alu alu_inst + ( + .m(ALUm), + .a(ALUIn1), + .b(ALUIn2), + .y(ALUResult), + .zf(ALUZero) + //.cf(), + //.of() + ); + + // datapath -- main + always @ (*) begin + case (IorD) + 0: mem_addr = pc; + 1: mem_addr = ALUOut; + endcase + case (RegDst) + 0: WriteRegister = instruction[20:16]; + 1: WriteRegister = instruction[15:11]; + 2: WriteRegister = 5'b11111; + endcase + case (RegSrc) + 0: WriteData = ALUOut; + 1: WriteData = mdr; + 2: WriteData = {instruction[15:0], 16'b0}; + 3: WriteData = pc; + endcase + case (ALUSrcB) + 0: ALUIn2 = B; + 1: ALUIn2 = 4; + 2: ALUIn2 = imm; + 3: ALUIn2 = imm << 2; + endcase + case (ALUSrcA) + 0: ALUIn1 = pc; + 1: ALUIn1 = A; + endcase + case (PCSource) + 0: newpc = ALUResult; + 1: newpc = ALUOut; + 2: newpc = {pc[31:28], instruction[25:0], 2'b0}; + 3: newpc = A; + endcase + end + always @ (posedge clk) begin + if (rst) begin + pc <= 32'b0; + instruction <= 0; + mdr <= 0; + ALUOut <= 0; + A <= 0; + B <= 0; + end + else begin + A <= ReadData1; + B <= ReadData2; + ALUOut <= ALUResult; + mdr <= MemData; + if (PCWrite) pc <= newpc; + if (IRWrite) instruction <= MemData; + end + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu_control_unit.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu_control_unit.v" new file mode 100644 index 0000000..117851b --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu_control_unit.v" @@ -0,0 +1,202 @@ +`timescale 1ns / 1ps + +module control_unit + ( + input clk, + input rst, + input [31:0]instruction, + input ALUZero, + + output reg PCWrite, + output reg IorD, + output reg MemRead, + output reg MemWrite, + output reg [2:0]RegSrc, + output reg IRWrite, + output reg [2:0]PCSource, + output reg [2:0]ALUm, + output reg ALUSrcA, + output reg [1:0]ALUSrcB, + output reg RegWrite, + output reg [1:0]RegDst + ); + + // control unit FSM state names + reg [7:0]phase = IF; + localparam IF = 0; + localparam ID_RF = 1; + localparam MEM_ADDR_CALC = 2; + localparam MEM_ACCESS_LW = 3; + localparam WB = 4; + localparam MEM_ACCESS_SW = 5; + localparam ADDI_END = 12; + localparam R_EX = 6; + localparam R_END = 7; + localparam BEQ_END = 8; + localparam J_END = 9; + localparam JAL_END = 10; + localparam JR_END = 11; + localparam LUI_END = 13; + localparam I_MFC0_END = 14; + //localparam I_MTC0_END = 15; + localparam I_ERET_END = 16; + localparam I_SYSCALL_END = 17; + localparam I_INT_END = 18; + localparam BAD = 99; + + // instruction[31:26] instruction type + wire [5:0]instr_type = instruction[31:26]; + localparam TYPE_REG = 6'b000000; + localparam TYPE_ADDI = 6'b001000; + localparam TYPE_LUI = 6'b001111; + localparam TYPE_LW = 6'b100011; + localparam TYPE_SW = 6'b101011; + localparam TYPE_BEQ = 6'b000100; + localparam TYPE_J = 6'b000010; + localparam TYPE_JAL = 6'b000011; + localparam TYPE_BAD = 0; + + // instruction[5:0] function + wire [5:0]instr_funct = instruction[5:0]; + localparam FUNCT_ADD = 6'b100000; + localparam FUNCT_SUB = 6'b100010; + localparam FUNCT_AND = 6'b100100; + localparam FUNCT_OR = 6'b100101; + localparam FUNCT_SLT = 6'b101010; + localparam FUNCT_JR = 6'b001000; + + // instruction label + reg [31:0]Op; + localparam OP_ADD = 91001; + localparam OP_SUB = 91001; + localparam OP_AND = 91001; + localparam OP_OR = 91001; + localparam OP_SLT = 91001; + localparam OP_ADDI = 90002; + localparam OP_LUI = 90003; + localparam OP_LW = 90004; + localparam OP_SW = 90005; + localparam OP_BEQ = 90006; + localparam OP_J = 90007; + localparam OP_JAL = 90008; + localparam OP_JR = 90009; + localparam OP_NOP = 91000; + localparam OP_BAD = 99000; + + // instruction decoding + always @ (*) begin + Op = OP_BAD; + case (instr_type) + TYPE_REG: case (instr_funct) + FUNCT_ADD: Op = OP_ADD; + FUNCT_SUB: Op = OP_SUB; + FUNCT_AND: Op = OP_AND; + FUNCT_OR: Op = OP_OR; + FUNCT_SLT: Op = OP_SLT; + FUNCT_JR: Op = OP_JR; + default: ; + endcase + TYPE_ADDI: Op = OP_ADDI; + TYPE_LUI: Op = OP_LUI; + TYPE_LW: Op = OP_LW; + TYPE_SW: Op = OP_SW; + TYPE_BEQ: Op = OP_BEQ; + TYPE_J: Op = OP_J; + TYPE_JAL: Op = OP_JAL; + default: ; + endcase + if (instruction == 32'b0) Op = OP_NOP; + end + + // control fsm + always @ (posedge clk) begin + if (rst) begin + phase <= IF; + end + else begin + case(phase) + IF: phase <= ID_RF; + ID_RF: begin + case(Op) + OP_NOP: phase <= IF; + + OP_LW: phase <= MEM_ADDR_CALC; + OP_SW: phase <= MEM_ADDR_CALC; + OP_ADDI: phase <= MEM_ADDR_CALC; + OP_LUI: phase <= LUI_END; + + OP_ADD: phase <= R_EX; + OP_SUB: phase <= R_EX; + OP_AND: phase <= R_EX; + OP_OR: phase <= R_EX; + + OP_BEQ: phase <= BEQ_END; + + OP_J: phase <= J_END; + OP_JAL: phase <= JAL_END; + OP_JR: phase <= JR_END; + default: phase <= BAD; + endcase + end + MEM_ADDR_CALC: case (Op) + OP_LW: phase <= MEM_ACCESS_LW; + OP_SW: phase <= MEM_ACCESS_SW; + OP_ADDI: phase <= ADDI_END; + default: phase <= BAD; + endcase + MEM_ACCESS_LW: phase <= WB; + WB: phase <= IF; + MEM_ACCESS_SW: phase <= IF; + ADDI_END: phase <= IF; + LUI_END: phase <= IF; + R_EX: phase <= R_END; + R_END: phase <= IF; + BEQ_END: phase <= IF; + J_END: phase <= IF; + JAL_END: phase <= IF; + JR_END: phase <= IF; + default: phase <= BAD; + endcase + end + end + + // control signals for each FSM states + always @ (*) begin + PCWrite = 0; + IorD = 0; + MemRead = 0; + MemWrite = 0; + RegSrc = 3'b000; + IRWrite = 0; + PCSource = 3'b000; + ALUm = 3'b000; + ALUSrcA = 0; + ALUSrcB = 0; + RegWrite = 0; + RegDst = 2'b00; + case (phase) + IF: begin MemRead = 1; ALUSrcB = 2'b01; IRWrite = 1; PCWrite = 1; end + ID_RF: ALUSrcB = 2'b11; + MEM_ADDR_CALC: begin ALUSrcA = 1; ALUSrcB = 2'b10; end + MEM_ACCESS_LW: begin MemRead = 1; IorD = 1; end + ADDI_END: begin RegWrite = 1; end + LUI_END: begin RegWrite = 1; RegSrc = 3'b010; end + WB: begin RegWrite = 1; RegSrc = 3'b001; end + MEM_ACCESS_SW: begin IorD = 1; MemWrite = 1; end + R_EX: begin + ALUSrcA = 1; + case (Op) + OP_ADD: ALUm = 3'b000; + OP_SUB: ALUm = 3'b001; + OP_AND: ALUm = 3'b010; + OP_OR: ALUm = 3'b011; + endcase + end + R_END: begin RegWrite = 1; RegDst = 2'b01; end + BEQ_END: begin ALUSrcA = 1; ALUm = 3'b001; PCWrite = ALUZero; PCSource = 3'b001; end + J_END: begin PCWrite = 1; PCSource = 3'b010; end + JAL_END: begin PCWrite = 1; PCSource = 3'b010; RegWrite = 1; RegDst = 2'b10; RegSrc = 3'b011; end + JR_END: begin PCWrite = 1; PCSource = 3'b011; end + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/debounce.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/debounce.v" new file mode 100644 index 0000000..8c91b2d --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/debounce.v" @@ -0,0 +1,77 @@ +`timescale 1ns / 1ps +// input button debounce +// https://timetoexplore.net/blog/arty-fpga-verilog-03 + +module debounce + #(parameter N = 2) + ( + input clk, + input [N-1:0]i_btn, + output reg [N-1:0]o_state = 0 + //output o_ondn, + //output o_onup + ); + + // sync with clock and combat metastability + reg [N-1:0]sync_0 = 0; + reg [N-1:0]sync_1 = 0; + always @(posedge clk) sync_0 <= i_btn; + always @(posedge clk) sync_1 <= sync_0; + + // 2.6 ms counter at 100 MHz + reg [18:0] counter; + wire idle = (o_state == sync_1); + wire [18:0]max = 10; + + always @(posedge clk) + begin + if (idle) + counter <= 0; + else + begin + counter <= counter + 1; + if (counter == max) + o_state <= sync_1; + end + end + + //assign o_ondn = ~idle & max & ~o_state; + //assign o_onup = ~idle & max & o_state; +endmodule +//module debounce + //#(parameter N = 4) + //( + //input clk, + //input [N-1:0]i_btn, + //output reg [N-1:0]o_state = 0 + ////output o_ondn, + ////output o_onup + //); + + //// sync with clock and combat metastability + //reg [N-1:0]sync_0 = 0; + //reg [N-1:0]sync_1 = 0; + //always @(posedge clk) sync_0 <= i_btn; + //always @(posedge clk) sync_1 <= sync_0; + + //// 2.6 ms(*2) counter at 100 MHz + //reg [18:0] counter = 0; + ////reg [19:0] counter; + //wire idle = (o_state == sync_1); + + //always @(posedge clk) + //begin + //if (idle) + //counter <= 0; + //else + //begin + //counter <= counter + 1; + //if (counter == 19'b11111) + ////o_state <= ~o_state; + //o_state <= sync_1; + //end + //end + + ////assign o_ondn = ~idle & max & ~o_state; + ////assign o_onup = ~idle & max & o_state; +//endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/dummy.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/dummy.v" new file mode 100644 index 0000000..a2029d0 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/dummy.v" @@ -0,0 +1,12 @@ +`timescale 1ns / 1ps +// dummy PL test on ebaz4205 +// 2020 COD Lab 6 +// ustcpetergu + +module dummy( + output led_g, + output led_r + ); + assign led_g = 1; + assign led_r = 0; +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/gpio.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/gpio.v" new file mode 100644 index 0000000..a818097 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/gpio.v" @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps + +module gpio + ( + input clk, + input rst, + input [1:0]a, + input [31:0]d, + input we, + output reg [31:0]spo, + + input [1:0]btn, + output reg [1:0]led + ); + + always @ (*) begin + case (a) + 0: spo = {31'b0, btn[0]}; + 1: spo = {31'b0, btn[1]}; + 2: spo = {31'b0, led[0]}; + 3: spo = {31'b0, led[1]}; + default: spo = 32'b0; + endcase + end + + always @ (posedge clk) begin + if (rst) begin + led <= 2'b11; + end + else if (we) begin + case (a) + 2: led[0] <= d[0]; + 3: led[1] <= d[0]; + default: ; + endcase + end + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/helloworldtest.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/helloworldtest.v" new file mode 100644 index 0000000..8a57b91 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/helloworldtest.v" @@ -0,0 +1,29 @@ +`timescale 1ns / 1ps +// helloworld test on ebaz4205 +// 2020 COD Lab 6 +// ustcpetergu + +module helloworldtest( + input clk, + + input btndata1, + input btndata2, + + output led_g, + output led_r, + output reg leddata1, + output reg leddata2 + ); + + reg [24:0]count = 0; + always @ (posedge clk) begin + count <= count + 1; + end + assign led_g = count[24]; + assign led_r = !count[24]; + + always @ (posedge clk) begin + leddata1 <= btndata1; + leddata2 <= btndata2; + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/mmapper.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/mmapper.v" new file mode 100644 index 0000000..dd4205c --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/mmapper.v" @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps + +module mmapper + ( + input [31:0]a, + input [31:0]d, + //input [31:0]dpra, + input we, + output reg [31:0]spo, + //output reg [31:0]dpo = 0, + + // 1024*32(4KB) boot rom: 0x00000000 + output reg [8:0]bootm_a, + output reg [31:0]bootm_d, + output reg bootm_we, + input [31:0]bootm_spo, + + // main memory: 0x10000000 + output reg [8:0]mainm_a, + output reg [31:0]mainm_d, + output reg mainm_we, + input [31:0]mainm_spo, + + // gpio: 0x20000000 + output reg [1:0]gpio_a, + output reg [31:0]gpio_d, + output reg gpio_we, + input [31:0]gpio_spo, + + // fifo uart: + // write 0x30000000 + // full 0x30000004 + // empty 0x30000008 + output reg [2:0]uart_a, + output reg [31:0]uart_d, + output reg uart_we, + input [31:0]uart_spo + ); + + always @ (*) begin + bootm_a = a[10:2]; + bootm_d = d; + mainm_a = a[10:2]; + mainm_d = d; + gpio_a = a[3:2]; + gpio_d = d; + uart_a = a[4:2]; + uart_d = d; + end + + always @ (*) begin + bootm_we = 0; + mainm_we = 0; + gpio_we = 0; + uart_we = 0; + case (a[31:28]) + 0: begin spo = bootm_spo; bootm_we = we; end + 1: begin spo = mainm_spo; mainm_we = we; end + 2: begin spo = gpio_spo; gpio_we = we; end + 3: begin spo = uart_spo; uart_we = we; end + default: ; + endcase + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/register_file.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/register_file.v" new file mode 100644 index 0000000..ca528a7 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/register_file.v" @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps +// pCPU regfile with debug port + +module register_file + #(parameter WIDTH = 32) + ( + input clk, + input [4:0]ra0, + input [4:0]ra1, + input [4:0]ra2, + input [4:0]wa, + input we, + input [WIDTH-1:0]wd, + output reg [WIDTH-1:0]rd0, + output reg [WIDTH-1:0]rd1, + output reg [WIDTH-1:0]rd2 + ); + + reg [WIDTH-1:0]regfile[31:0]; + initial $readmemh("/home/petergu/MyHome/pComputer/pCPU/regfile.dat", regfile); + + always @ (*) begin + if (ra0 == 5'b0) rd0 = 0; + else rd0 = regfile[ra0]; + if (ra1 == 5'b0) rd1 = 0; + else rd1 = regfile[ra1]; + if (ra2 == 5'b0) rd2 = 0; + else rd2 = regfile[ra2]; + end + + always @ (posedge clk) begin + if (we) begin + if (wa != 5'b0) begin + regfile[wa] <= wd; + end + end + end + +endmodule + diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/uart.v" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/uart.v" new file mode 100644 index 0000000..887d687 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/uart.v" @@ -0,0 +1,175 @@ +`timescale 1ns / 1ps +// pComputer UART I/O +// input XXMHz, 16x oversampling +// warning: not very reliable: read/write together case, ... +// so need special software care(better to write one value and wait until idle) +// +// write 0x00: transmit data +// read 0x00: received data +// write 0x01: begin receiving +// read 0x01: receive done? +// read 0x02: transmit done? +// *need to x4 these addresses in assembly! + +module uart + ( + input clk, + input rst, + + input [2:0]a, + input [31:0]d, + input we, + output reg [31:0]spo, + + //output wire read_enabled_out, + //output wire rx_state_out0, + //output wire rx_state_out1, + + input rx, + output reg tx = 1 + ); + + wire rxclk_en; + wire txclk_en; + baud_rate_gen baud_rate_gen_inst + ( + .clk(clk), + .rst(rst), + .rxclk_en(rxclk_en), + .txclk_en(txclk_en) + ); + + localparam IDLE = 3'b000; + //localparam PREPARE1 = 3'b001; + //localparam PREPARE2 = 3'b010; + localparam START = 3'b011; + localparam DATA = 3'b100; + localparam STOP = 3'b101; + reg [2:0]state_tx = IDLE; + reg [7:0]data_tx = 8'h00; + reg [2:0]bitpos_tx = 0; + + localparam RX_STATE_START = 2'b01; + localparam RX_STATE_DATA = 2'b10; + localparam RX_STATE_STOP = 2'b11; + reg [1:0]state_rx = RX_STATE_START; + //assign rx_state_out0 = state_rx[0]; + //assign rx_state_out1 = state_rx[1]; + reg [3:0]sample = 0; + reg [3:0]bitpos_rx = 0; + reg [7:0]scratch = 8'b0; + + reg read_enabled = 0; + reg [7:0]data_rx = 0; + //reg [7:0]data_rx_ready = 0; + + always @ (*) begin + if (a == 3'b000) spo = {24'b0, data_rx}; + else if (a == 3'b001) spo = {31'b0, !read_enabled}; + else if (a == 3'b010) spo = {31'b0, (state_tx == IDLE)}; + else spo = 32'b0; + end + always @ (posedge clk) begin + if (rst) begin + tx <= 1'b1; + data_tx <= 0; + bitpos_tx <= 0; + state_tx <= IDLE; + + data_rx <= 0; + read_enabled <= 0; + //data_rx_ready <= 0; + state_rx <= RX_STATE_START; + sample <= 0; + end + else begin + //if (we) begin + //if (a == 3'b011 & d[0]) begin + //// so no way to set this to 0(cancel reading)! + //read_enabled <= 1; + //end + //if (a == 3'b000 & !fifo_full) begin + //if (a == 3'b000 & !tx_write) begin + ////fifo_enqueue <= 1; + ////fifo_in <= d[7:0]; + //data_tx <= d[7:0]; + //end + //else begin + //fifo_enqueue <= 0; + //fifo_in <= 8'b0; + //end + //end + case (state_tx) + IDLE: if (we & (a == 3'b000)) begin + data_tx <= d[7:0]; + state_tx <= START; + end + START: if (txclk_en) begin + bitpos_tx <= 0; + tx <= 1'b0; + state_tx <= DATA; + end + DATA: if (txclk_en) begin + if (bitpos_tx == 7) state_tx <= STOP; + else bitpos_tx <= bitpos_tx + 1; + tx <= data_tx[bitpos_tx]; + end + STOP: if (txclk_en) begin + tx <= 1'b1; + state_tx <= IDLE; + end + default: ; + endcase + + if (we & a == 3'b001) begin + read_enabled <= 1; + end + else if (rxclk_en) begin + case (state_rx) + /* + Start counting from the first low sample, once we've + sampled a full bit, start collecting data bits. + */ + RX_STATE_START: begin + //data_rx_ready <= 0; + if (!rx || sample != 0) sample <= sample + 1; + if (sample == 15) begin + state_rx <= RX_STATE_DATA; + bitpos_rx <= 0; + sample <= 0; + scratch <= 0; + end + end + RX_STATE_DATA: begin + sample <= sample + 1; + if (sample == 8) begin + scratch[bitpos_rx[2:0]] <= rx; + bitpos_rx <= bitpos_rx + 1; + end + if (bitpos_rx == 8 && sample == 15) state_rx <= RX_STATE_STOP; + end + /* + Our baud clock may not be running at exactly the + same rate as the transmitter. If we thing that + we're at least half way into the stop bit, allow + transition into handling the next start bit. + */ + RX_STATE_STOP: begin + if (sample == 15 || (sample >= 8 && !rx)) begin + state_rx <= RX_STATE_START; + data_rx <= scratch; + //data_rx_ready <= 1; + read_enabled <= 0; + sample <= 0; + end else begin + sample <= sample + 1; + end + end + default: state_rx <= RX_STATE_START; + endcase + end + + + end + end +endmodule diff --git "a/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6.tcl" "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6.tcl" new file mode 100644 index 0000000..16fb188 --- /dev/null +++ "b/\350\256\241\347\256\227\346\234\272\347\273\204\346\210\220\345\216\237\347\220\206/codes/ustcpetergu/lab6/lab6.tcl" @@ -0,0 +1,1304 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1 (64-bit) +# +# lab6.tcl: Tcl script for re-creating project 'lab6-softcore-on-ebaz4205' +# +# Generated by Vivado on Fri Jul 10 16:30:44 CST 2020 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (lab6.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/hdl/bd_hello_wrapper.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/alu.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu_control_unit.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/register_file.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu-multi-cycle.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/gpio.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/mmapper.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/clock_div_pulse.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/uart.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/debounce.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_main/hdl/bd_main_wrapper.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/helloworldtest.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/dummy.v" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/ip/bd_hello_bd_main_0_2/src/result_echo.coe" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/constrs_1/imports/lab6/ebaz4205.xdc" +# "/home/petergu/MyHome/COD/lab6/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sim_1/new/bd_main_simu.v" +# +# 3. The following remote source files that were added to the original project:- +# +# "/home/petergu/MyHome/COD/lab6/result_echo.coe" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "lab6-softcore-on-ebaz4205" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "lab6.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/lab6-softcore-on-ebaz4205"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z010clg400-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xc7z010clg400-1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "8" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "8" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "8" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "8" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "8" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "8" -objects $obj +set_property -name "webtalk.xcelium_export_sim" -value "2" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "8" -objects $obj +set_property -name "webtalk.xsim_launch_sim" -value "5" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/lab6-softcore-on-ebaz4205/ip"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/result_echo.coe"] \ +] +add_files -norecurse -fileset $obj $files + +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/hdl/bd_hello_wrapper.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/alu.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu_control_unit.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/register_file.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/cpu-multi-cycle.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/gpio.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/mmapper.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/clock_div_pulse.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/uart.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/debounce.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_main/hdl/bd_main_wrapper.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/helloworldtest.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/new/dummy.v" ]\ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sources_1/bd/bd_hello/ip/bd_hello_bd_main_0_2/src/result_echo.coe" ]\ +] +set imported_files [import_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "src/result_echo.coe" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "used_in" -value "" -objects $file_obj +set_property -name "used_in_simulation" -value "0" -objects $file_obj +set_property -name "used_in_synthesis" -value "0" -objects $file_obj + + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "bd_hello_wrapper" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize ${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/constrs_1/imports/lab6/ebaz4205.xdc]" +set file_imported [import_files -fileset constrs_1 [list $file]] +set file "lab6/ebaz4205.xdc" +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "target_part" -value "xc7z010clg400-1" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Import local files from the original project +set files [list \ + [file normalize "${origin_dir}/lab6-softcore-on-ebaz4205/lab6-softcore-on-ebaz4205.srcs/sim_1/new/bd_main_simu.v" ]\ +] +set imported_files [import_files -fileset sim_1 $files] + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "top_simu" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj +set_property -name "xsim.simulate.log_all_signals" -value "1" -objects $obj +set_property -name "xsim.simulate.saif_all_signals" -value "1" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + + +# Adding sources referenced in BDs, if not already added + + +# Proc to create BD bd_hello +proc cr_bd_bd_hello { parentCell } { + + # CHANGE DESIGN NAME HERE + set design_name bd_hello + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + set bCheckIPsPassed 1 + ################################################################## + # CHECK IPs + ################################################################## + set bCheckIPs 1 + if { $bCheckIPs == 1 } { + set list_check_ips "\ + user.org:user:bd_main:1.0\ + xilinx.com:ip:processing_system7:5.5\ + xilinx.com:ip:xlconcat:2.1\ + " + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + + } + + if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 + } + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + set MDIO_ETHERNET_0_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 MDIO_ETHERNET_0_0 ] + + + # Create ports + set ENET0_GMII_RX_CLK_0 [ create_bd_port -dir I -type clk ENET0_GMII_RX_CLK_0 ] + set ENET0_GMII_RX_DV_0 [ create_bd_port -dir I ENET0_GMII_RX_DV_0 ] + set ENET0_GMII_TX_CLK_0 [ create_bd_port -dir I -type clk ENET0_GMII_TX_CLK_0 ] + set ENET0_GMII_TX_EN_0 [ create_bd_port -dir O -from 0 -to 0 ENET0_GMII_TX_EN_0 ] + set btndata [ create_bd_port -dir I -from 1 -to 0 btndata ] + set enet0_gmii_rxd [ create_bd_port -dir I -from 3 -to 0 enet0_gmii_rxd ] + set enet0_gmii_txd [ create_bd_port -dir O -from 3 -to 0 enet0_gmii_txd ] + set leddata [ create_bd_port -dir O -from 1 -to 0 leddata ] + set uart_rx [ create_bd_port -dir I uart_rx ] + set uart_tx [ create_bd_port -dir O uart_tx ] + + # Create instance: bd_main_0, and set properties + set bd_main_0 [ create_bd_cell -type ip -vlnv user.org:user:bd_main:1.0 bd_main_0 ] + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {25.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CLK0_FREQ {125000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x0FFFFFFF} \ + CONFIG.PCW_ENET0_ENET0_IO {EMIO} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ + CONFIG.PCW_ENET0_GRP_MDIO_IO {EMIO} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {5} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {0} \ + CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_ENET0 {1} \ + CONFIG.PCW_EN_EMIO_ENET1 {0} \ + CONFIG.PCW_EN_EMIO_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ + CONFIG.PCW_EN_ENET0 {1} \ + CONFIG.PCW_EN_ENET1 {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SDIO1 {0} \ + CONFIG.PCW_EN_SMC {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {4} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {125} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ + CONFIG.PCW_MIO_0_DIRECTION {out} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_10_DIRECTION {inout} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_10_PULLUP {enabled} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_DIRECTION {inout} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_11_PULLUP {enabled} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_DIRECTION {inout} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_12_PULLUP {enabled} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_DIRECTION {inout} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_13_PULLUP {enabled} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_14_DIRECTION {in} \ + CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_14_PULLUP {enabled} \ + CONFIG.PCW_MIO_14_SLEW {slow} \ + CONFIG.PCW_MIO_24_DIRECTION {out} \ + CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_24_PULLUP {enabled} \ + CONFIG.PCW_MIO_24_SLEW {slow} \ + CONFIG.PCW_MIO_25_DIRECTION {in} \ + CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_25_PULLUP {enabled} \ + CONFIG.PCW_MIO_25_SLEW {slow} \ + CONFIG.PCW_MIO_2_DIRECTION {out} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_3_DIRECTION {out} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_40_DIRECTION {inout} \ + CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_40_PULLUP {enabled} \ + CONFIG.PCW_MIO_40_SLEW {slow} \ + CONFIG.PCW_MIO_41_DIRECTION {inout} \ + CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_41_PULLUP {enabled} \ + CONFIG.PCW_MIO_41_SLEW {slow} \ + CONFIG.PCW_MIO_42_DIRECTION {inout} \ + CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_42_PULLUP {enabled} \ + CONFIG.PCW_MIO_42_SLEW {slow} \ + CONFIG.PCW_MIO_43_DIRECTION {inout} \ + CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_43_PULLUP {enabled} \ + CONFIG.PCW_MIO_43_SLEW {slow} \ + CONFIG.PCW_MIO_44_DIRECTION {inout} \ + CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_44_PULLUP {enabled} \ + CONFIG.PCW_MIO_44_SLEW {slow} \ + CONFIG.PCW_MIO_45_DIRECTION {inout} \ + CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_45_PULLUP {enabled} \ + CONFIG.PCW_MIO_45_SLEW {slow} \ + CONFIG.PCW_MIO_4_DIRECTION {inout} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_52_DIRECTION {out} \ + CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_52_PULLUP {enabled} \ + CONFIG.PCW_MIO_52_SLEW {slow} \ + CONFIG.PCW_MIO_53_DIRECTION {inout} \ + CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_53_PULLUP {enabled} \ + CONFIG.PCW_MIO_53_SLEW {slow} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_DIRECTION {inout} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_7_DIRECTION {out} \ + CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_7_PULLUP {disabled} \ + CONFIG.PCW_MIO_7_SLEW {slow} \ + CONFIG.PCW_MIO_8_DIRECTION {out} \ + CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_8_PULLUP {disabled} \ + CONFIG.PCW_MIO_8_SLEW {slow} \ + CONFIG.PCW_MIO_9_DIRECTION {inout} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {NAND Flash#unassigned#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#NAND Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 1#UART 1#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \ + CONFIG.PCW_MIO_TREE_SIGNALS {cs#unassigned#ale#we_b#data[2]#data[0]#data[1]#cle#re_b#data[4]#data[5]#data[6]#data[7]#data[3]#busy#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx#rx#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \ + CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ + CONFIG.PCW_NAND_NAND_IO {MIO 0 2.. 14} \ + CONFIG.PCW_NAND_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ + CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ + CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ + CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_SD1_SD1_IO {