Release v1.3.0 #418
Replies: 1 comment
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Upgrading from v1.2.0Due to significant system-level changes, existing users of
// Timing Manager events occur when the PWM carrier is low (a valley).
// You can replace 'low' with 'high' or 'both' if needed.
timing_manager_trigger_on_pwm_low();
// Set the control task execution frequency by giving the Timing Manager a sub-rate ratio of the PWM Carrier Frequency
// i.e. If you are switching at 100 kHz and want sampling and control code to execute at 10 kHz (1/10 the PWM freq), set the Timing Manager ratio to 10
timing_manager_set_ratio(10);
// Connect Eddy Current Sensor to GPIO Port 1 on REV D... you likely already have a similar line
gpio_mux_set_device(GPIO_MUX_BASE_ADDR, GPIO_MUX_DEVICE1)
// OR
// Connect Eddy Current Sensor to GPIO Port 1 on REV E/F... you likely already have a similar line
gp3io_mux_set_device(GP3IO_MUX_1_BASE_ADDR, GP3IO_MUX_DEVICE2)
// NEW: Enable Eddy Current Sensor connected to GPIO Port 1 in the Timing Manager (Any REV)
// (You will have to add this function for each sensor interface you are using)
timing_manager_enable_sensor(EDDY_1);
Further SupportIf you have further questions, the following documentation created for this release may be useful: |
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AMDC Firmware Release: v1.3.0
v1.3.0
has been released, making the default GitHub branchv1.3.x
. Please see the changes below.For users upgrading from
v1.2.0
to the latest release, a comment has been left below on this page which details the steps needed to make your code compatible.Changes in this release:
Timing Manager & Scheduler
uint32_t
todouble
type, added tolerance marginSensor Interfaces
motherboard
toamds
SYNC_TX
interrupt from AMDS IPFPGA Changes
xparameters.h
Miscellaneous
Release Information
The main feature of release
v1.3.0
is the updates made to timing and synchronization of key control events (sensor feedback and control task execution), particularly for high-speed research projects. This new timing synchronization is done via a new system-level FPGA peripheral, called the "Timing Manager". The Timing Manager synchronizes all sensor feedback and code execution to the peaks and valleys of the PWM switching carrier. Users can configure the timing manager to sample sensors and execute their code at an integer sub-rate of the PWM carrier.This release also adds new control options to the Inverter/PowerStack interface. Users can configure newly-calculated duty ratios to be flushed out immediately, at the next PWM carrier peak/valley (as done in
v.1.2.0
), or at the next Timing Manager trigger event (recommended). Also added is the ability to enable/disable or invert the gate drive signals to each individual half-bridge.Finally, GPIO port number indexing has been standardized to start at 1 across hardware REV D, E, and F, in both the C driver and command interface.
Contributors
Thanks to the following contributors in this release:
This discussion was created from the release v1.3.0.
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