diff --git a/src/main/scala/yunsuan/fpu/FloatAdder.scala b/src/main/scala/yunsuan/fpu/FloatAdder.scala
index 24fc264..cfb13fb 100644
--- a/src/main/scala/yunsuan/fpu/FloatAdder.scala
+++ b/src/main/scala/yunsuan/fpu/FloatAdder.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpu
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.vector._
 import yunsuan.{FaddOpCode, VectorElementFormat}
diff --git a/src/main/scala/yunsuan/fpu/FloatFMA.scala b/src/main/scala/yunsuan/fpu/FloatFMA.scala
index 8a92f15..90114f8 100644
--- a/src/main/scala/yunsuan/fpu/FloatFMA.scala
+++ b/src/main/scala/yunsuan/fpu/FloatFMA.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpu
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.FmaOpCode
 import yunsuan.util.GatedValidRegNext
diff --git a/src/main/scala/yunsuan/fpulite/FloatAdder.scala b/src/main/scala/yunsuan/fpulite/FloatAdder.scala
index 3226764..d13b44f 100644
--- a/src/main/scala/yunsuan/fpulite/FloatAdder.scala
+++ b/src/main/scala/yunsuan/fpulite/FloatAdder.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpulite
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.vector._
 import yunsuan.{VfaddOpCode, VectorElementFormat}
diff --git a/src/main/scala/yunsuan/fpulite/FloatFMA.scala b/src/main/scala/yunsuan/fpulite/FloatFMA.scala
index 13d7626..19981e1 100644
--- a/src/main/scala/yunsuan/fpulite/FloatFMA.scala
+++ b/src/main/scala/yunsuan/fpulite/FloatFMA.scala
@@ -1,6 +1,5 @@
 package yunsuan.fpulite
 import chisel3._
-import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import chisel3.util._
 import yunsuan.FmaOpCode
 import yunsuan.util.GatedValidRegNext