From 79b2afdc66db97ade3221de7a09b611bbb4ef594 Mon Sep 17 00:00:00 2001
From: sinceforYy <1017657683@qq.com>
Date: Mon, 4 Mar 2024 11:37:43 +0800
Subject: [PATCH] test: add enable to RegNext

---
 src/test/scala/top/VectorSimTop.scala              | 3 +++
 src/test/scala/vector/VFCvtWapper.scala            | 3 ++-
 src/test/scala/vector/VectorALU/VIMac64bSpec.scala | 1 +
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/test/scala/top/VectorSimTop.scala b/src/test/scala/top/VectorSimTop.scala
index e66fbdf..cf00b00 100644
--- a/src/test/scala/top/VectorSimTop.scala
+++ b/src/test/scala/top/VectorSimTop.scala
@@ -150,6 +150,7 @@ class SimTop() extends VPUTestModule {
     val vcvt = Module(new VectorCvt(XLEN))
 
     require(vfa.io.fp_a.getWidth == XLEN)
+    vfa.io.fire := io.in.valid
     vfa.io.fp_a := src1
     vfa.io.fp_b := src2
     //io.widen_a Cat(vs2(95,64),vs2(31,0)) or Cat(vs2(127,96),vs2(63,32))
@@ -229,6 +230,7 @@ class SimTop() extends VPUTestModule {
     via_result.fflags(i) := 0.U // DontCare
     via_result.vxsat := 0.U // DontCare
 
+    vff.io.fire := io.in.valid
     vff.io.fp_a := src1
     vff.io.fp_b := src2
     vff.io.fp_c := src3
@@ -252,6 +254,7 @@ class SimTop() extends VPUTestModule {
     vff_result.vxsat := 0.U // DontCare
 
     // connect vcvt's io
+    vcvt.io.fire := io.in.valid
     vcvt.io.sew := sew
     vcvt.io.opType := opcode
     vcvt.io.rm := rm
diff --git a/src/test/scala/vector/VFCvtWapper.scala b/src/test/scala/vector/VFCvtWapper.scala
index 11f05d0..cbc4172 100644
--- a/src/test/scala/vector/VFCvtWapper.scala
+++ b/src/test/scala/vector/VFCvtWapper.scala
@@ -7,13 +7,14 @@ import yunsuan.vector.VectorConvert.{VectorCvt, VectorCvtIO}
 
 class VFCVTTop(xlen :Int) extends Module{
   val io = IO(new VectorCvtIO(xlen))
-  val (src, opType, sew, rm) = (io.src, io.opType, io.sew, io.rm)
+  val (fire, src, opType, sew, rm) = (io.fire, io.src, io.opType, io.sew, io.rm)
   val vfcvtWrapper = Module(new VectorCvt(64))
 
   val inputNext = Wire(UInt(64.W))
   val inputReg = RegNext(inputNext,0.U)
   inputNext := src
 
+  vfcvtWrapper.io.fire := fire
   vfcvtWrapper.io.src := inputReg
   vfcvtWrapper.io.opType := opType
   vfcvtWrapper.io.sew := sew
diff --git a/src/test/scala/vector/VectorALU/VIMac64bSpec.scala b/src/test/scala/vector/VectorALU/VIMac64bSpec.scala
index 00ce442..017a2f3 100644
--- a/src/test/scala/vector/VectorALU/VIMac64bSpec.scala
+++ b/src/test/scala/vector/VectorALU/VIMac64bSpec.scala
@@ -36,6 +36,7 @@ class VIMac64bWrapper extends Module {
   })
 
   val vIMac = Module(new VIMac64b)
+  vIMac.io.fire := io.in.valid
   vIMac.io.info := io.in.bits.info
   vIMac.io.srcType := io.in.bits.srcType
   vIMac.io.vdType := io.in.bits.vdType