From 109ce2016df046f6faedbe8135ba5bc08aa4f458 Mon Sep 17 00:00:00 2001 From: lewislzh Date: Sat, 21 Dec 2024 00:33:36 +0800 Subject: [PATCH] fix(fma): Fix the misuse of pipeline registers --- src/main/scala/yunsuan/fpu/FloatFMA.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/yunsuan/fpu/FloatFMA.scala b/src/main/scala/yunsuan/fpu/FloatFMA.scala index 00c100a..fdc57b5 100644 --- a/src/main/scala/yunsuan/fpu/FloatFMA.scala +++ b/src/main/scala/yunsuan/fpu/FloatFMA.scala @@ -476,9 +476,9 @@ class FloatFMA() extends Module{ Mux(is_fp32_reg1, fraction_result_no_round_f32_reg_d, fraction_result_no_round_f16_reg_d)) val fraction_result_no_round_reg = RegEnable(fraction_result_no_round_reg_d, fire_reg1) - val fraction_result_no_round_f64_reg2 = fraction_result_no_round_reg_d - val fraction_result_no_round_f32_reg2 = fraction_result_no_round_reg_d(22,0) - val fraction_result_no_round_f16_reg2 = fraction_result_no_round_reg_d(9,0) + val fraction_result_no_round_f64_reg2 = fraction_result_no_round_reg + val fraction_result_no_round_f32_reg2 = fraction_result_no_round_reg(22,0) + val fraction_result_no_round_f16_reg2 = fraction_result_no_round_reg(9,0) val fraction_result_round_f64 = fraction_result_no_round_f64_reg2 +& 1.U val fraction_result_round_f32 = fraction_result_no_round_f32_reg2 +& 1.U