DDR initialize code is very slow: 4.5 seconds

[tpetazzoni]

I'm using mv-ddr-marvell as of commit 618dadd and arm-trusted-firmware as of commit 9484123bfe29011ed44b717a23eb53a70b97ce3d. The DDR initialization is very slow as it takes 4.5 seconds, which is a lot of time on an overall system boot. Could this be optimized ?

See the following boot log. The first column is the absolute time, the second column is the time difference with the previous line:

[0.000000 0.000000] 
[0.000052 0.000052] BootROM - 2.03
[0.000201 0.000149] Starting CP-1 IOROM 1.07
[0.000412 0.000211] Booting from SPI NOR flash 1 (0x32)
[0.447029 0.446617] Found valid image at boot postion 0x000
[0.447447 0.000418] lNOTICE:  Starting binary extension
[0.447767 0.000320] NOTICE:  SVC: SW Revision 0x0. SVC is not supported
[0.472088 0.024321] mv_ddr: mv_ddr-devel-18.12.0-g04c1723585-dirty (Jan 09 2019 - 02:12:13 PM)
[4.983743 4.511655] mv_ddr: completed successfully
[4.999766 0.016023] NOTICE:  Cold boot
[5.996553 0.996787] NOTICE:  Booting Trusted Firmware

This was tested on a MacchiatoBin, rev 1.3.

[pali]

@tpetazzoni Thomas, could you check if latest mv_ddr from git master branch has still this issue?

[tpetazzoni]

I'm afraid, but I'm no longer actively working on Marvell platforms these days, so I don't think I will have the time to see if this issue is fixed. I guess it can be closed if you don't see the problem anymore.

[pali]

Well, I see that DDR4 training on other SoCs (A3720) is also slow (few seconds) compared to DDR3 training (basically immediately). So was I thinking if I'm the only one who see this problem and I found this ticket, which seems to confirm it.

[bschnei]

In case it's still (or becomes) relevant to anyone, I have an ESPRESSObin Ultra (A3720 DDR4) that has this issue. The slow DDR initialization appears related to changes made in the A3700-utils-marvell repo, not here.

The changes are related to 5 consecutive commits whose message is tagged with ddr_init that were committed in May 21, 2019 between versions 18.2.0 and 18.2.1, the first of which is here. Using copies of the sys_init/ddr files prior to those changes resolves the issue. I've applied this patch to the repo at a3e1c67 and the DDR init speed is far more reasonable.

The commit messages suggest the ddr_init changes were made were for stability reasons. I have not experienced any issues and have been using the faster code on my device for months. YMMV.