typedecode.vcd

$date
	Wed Aug 30 12:19:23 2023
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module decode_tb $end
$var wire 1 ! store_tb $end
$var wire 1 " r_tb $end
$var wire 1 # lui_tb $end
$var wire 1 $ load_tb $end
$var wire 1 % jalr_tb $end
$var wire 1 & jal_tb $end
$var wire 1 ' itype_tb $end
$var wire 1 ( branch_tb $end
$var reg 7 ) opcode_tb [6:0] $end
$scope module u_typedec1 $end
$var wire 7 * opcode [6:0] $end
$var reg 1 ( branch $end
$var reg 1 ' itype $end
$var reg 1 & jal $end
$var reg 1 % jalr $end
$var reg 1 $ load $end
$var reg 1 # lui $end
$var reg 1 " r $end
$var reg 1 ! store $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx *
bx )
x(
x'
x&
x%
x$
x#
x"
x!
$end
#10
0#
0&
0%
0'
0(
0!
0$
1"
b110011 )
b110011 *
#20
1$
0"
b11 )
b11 *
#30
1!
0$
b100011 )
b100011 *
#40
1(
0!
b1100011 )
b1100011 *
#50
1'
0(
b10011 )
b10011 *
#60
1%
0'
b110111 )
b110111 *
#70
1&
0%
b1101111 )
b1101111 *
#80
0&
1%
b110111 )
b110111 *
#90