diff --git a/SECURITY.md b/SECURITY.md
index 22101c1..b84a070 100644
--- a/SECURITY.md
+++ b/SECURITY.md
@@ -15,7 +15,7 @@ Instead, please report them to the repository maintainers by sending a **GPG
 encrypted e-mail** to _all maintainers of a specific repo_ using their GPG keys.
 
 A list of repository maintainers and their keys and e-mail addresses are 
-provided inside MAINTANERS.md file and MANIFEST.yml, with the latter also 
+provided inside MAINTAINERS.md file and MANIFEST.yml, with the latter also 
 included in the README.md as a manifest block, which looks in the following way:
 
 ```yaml
diff --git a/examples/rgb.rs b/examples/rgb.rs
index 0d7ce43..4e207cd 100644
--- a/examples/rgb.rs
+++ b/examples/rgb.rs
@@ -14,7 +14,7 @@ use aluvm::reg::{Reg32, RegA};
 /// Example extension set of operations which are required for RGB
 // TODO(#3) Move to RGB Core Library
 pub enum RgbOp {
-    /// Counts number of metatdata of specific type
+    /// Counts number of metadata of specific type
     CountMeta(u16, RegA, Reg32),
     CountState(u16, RegA, Reg32),
     CountRevealed(u16, RegA, Reg32),
diff --git a/src/isa/flags.rs b/src/isa/flags.rs
index 9c2d6fa..9f056b3 100644
--- a/src/isa/flags.rs
+++ b/src/isa/flags.rs
@@ -919,7 +919,7 @@ pub enum DeleteFlag {
     Zero = 1,
 
     /// Set destination to the fragment of the string `offset_start..src_len` if
-    /// `offset_end > src_len && offser_start <= src_len`.
+    /// `offset_end > src_len && offset_start <= src_len`.
     ///
     /// Matches case (3) in [`crate::isa::BytesOp::Del`] description
     #[display("c")]
@@ -927,7 +927,7 @@ pub enum DeleteFlag {
 
     /// Set destination to the fragment of the string `offset_start..src_len` and extend its length
     /// up to `offset_end - offset_start` with trailing zeros if
-    /// `offset_end > src_len && offser_start <= src_len`.
+    /// `offset_end > src_len && offset_start <= src_len`.
     ///
     /// Matches case (4) in [`crate::isa::BytesOp::Del`] description
     #[display("e")]
diff --git a/src/isa/instr.rs b/src/isa/instr.rs
index ba023b7..734b906 100644
--- a/src/isa/instr.rs
+++ b/src/isa/instr.rs
@@ -819,7 +819,7 @@ pub enum BytesOp {
     /// </pre>
     ///
     /// `flag1` and `flag2` arguments indicate whether `st0` should be set to `false` if
-    /// `offset_start > src_len` and `offset_end > src_len && offser_start <= src_len`.
+    /// `offset_start > src_len` and `offset_end > src_len && offset_start <= src_len`.
     /// In all other cases, `st0` value is not modified.
     #[display("del.{0}   {7},{8},{1}{2},{3}{4},{5},{6}")]
     Del(
@@ -830,7 +830,7 @@ pub enum BytesOp {
         /** `a8` or `a16` register index with a second offset for delete location */ Reg32,
         /** `flag1` indicating `st0` value set to false if `offset_start > src_len` */ bool,
         /** `flag2` indicating `st0` value set to false if
-         * `offset_end > src_len && offser_start <= src_len` */
+         * `offset_end > src_len && offset_start <= src_len` */
         bool,
         /** Source `s` register */ RegS,
         /** Destination `s` register */ RegS,
diff --git a/src/lib.rs b/src/lib.rs
index 9242651..d8d4ac4 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -54,7 +54,7 @@
 //! ## Design
 //!
 //! The robusness lies at the very core of AluVM. It is designed to avoid any
-//! undefined behaviour. Specificly,
+//! undefined behaviour. Specifically,
 //! * All registers may be in the undefined statel
 //! * Impossible/incorrect operations put destination register into a special *undefined state*;
 //! * Code always extended to 2^16 bytes with zeros, which corresponds to “set st0 register to false
diff --git a/src/reg/families.rs b/src/reg/families.rs
index 71475f5..47631da 100644
--- a/src/reg/families.rs
+++ b/src/reg/families.rs
@@ -529,7 +529,7 @@ impl TryFrom<RegAll> for RegR {
     fn try_from(value: RegAll) -> Result<Self, Self::Error> { value.reg_r().ok_or(()) }
 }
 
-/// Superset of all registers accessible via intstructions. The superset includes `A`, `F`, `R` and
+/// Superset of all registers accessible via instructions. The superset includes `A`, `F`, `R` and
 /// `S` families of registers.
 #[derive(Copy, Clone, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Display, From)]
 #[display(inner)]