From 1f52ba16526a4a948bf91485b8effe0e8571dae2 Mon Sep 17 00:00:00 2001
From: Dr Maxim Orlovsky <orlovsky@ubideco.org>
Date: Sat, 19 Oct 2024 01:22:23 +0200
Subject: [PATCH] lib: add Fail execution step

---
 src/isa/exec.rs    | 22 +++++++++++-----------
 src/isa/instr.rs   |  2 +-
 src/library/lib.rs |  7 +++++++
 3 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/src/isa/exec.rs b/src/isa/exec.rs
index 8701844..9196ac6 100644
--- a/src/isa/exec.rs
+++ b/src/isa/exec.rs
@@ -48,6 +48,9 @@ pub enum ExecStep {
     /// Stop program execution
     Stop,
 
+    /// Stop and fail program execution
+    Fail,
+
     /// Move to the next instruction
     Next,
 
@@ -227,37 +230,34 @@ impl InstructionSet for ControlFlowOp {
 
     fn exec(&self, regs: &mut CoreRegs, site: LibSite, _: &()) -> ExecStep {
         match self {
-            ControlFlowOp::Fail => {
-                regs.st0 = false;
-                ExecStep::Stop
-            }
+            ControlFlowOp::Fail => ExecStep::Fail,
             ControlFlowOp::Test => {
                 if regs.st0 {
                     ExecStep::Next
                 } else {
-                    ExecStep::Stop
+                    ExecStep::Fail
                 }
             }
             ControlFlowOp::Jmp(offset) => {
-                regs.jmp().map(|_| ExecStep::Jump(*offset)).unwrap_or(ExecStep::Stop)
+                regs.jmp().map(|_| ExecStep::Jump(*offset)).unwrap_or(ExecStep::Fail)
             }
             ControlFlowOp::Jif(offset) => {
                 if regs.st0 {
-                    regs.jmp().map(|_| ExecStep::Jump(*offset)).unwrap_or(ExecStep::Stop)
+                    regs.jmp().map(|_| ExecStep::Jump(*offset)).unwrap_or(ExecStep::Fail)
                 } else {
                     ExecStep::Next
                 }
             }
             ControlFlowOp::Routine(offset) => {
-                regs.call(site).map(|_| ExecStep::Jump(*offset)).unwrap_or(ExecStep::Stop)
+                regs.call(site).map(|_| ExecStep::Jump(*offset)).unwrap_or(ExecStep::Fail)
             }
             ControlFlowOp::Call(site) => {
-                regs.call(*site).map(|_| ExecStep::Call(*site)).unwrap_or(ExecStep::Stop)
+                regs.call(*site).map(|_| ExecStep::Call(*site)).unwrap_or(ExecStep::Fail)
             }
             ControlFlowOp::Exec(site) => {
-                regs.jmp().map(|_| ExecStep::Call(*site)).unwrap_or(ExecStep::Stop)
+                regs.jmp().map(|_| ExecStep::Call(*site)).unwrap_or(ExecStep::Fail)
             }
-            ControlFlowOp::Ret => regs.ret().map(ExecStep::Call).unwrap_or(ExecStep::Stop),
+            ControlFlowOp::Ret => regs.ret().map(ExecStep::Call).unwrap_or(ExecStep::Fail),
         }
     }
 }
diff --git a/src/isa/instr.rs b/src/isa/instr.rs
index 52df35e..d8485cd 100644
--- a/src/isa/instr.rs
+++ b/src/isa/instr.rs
@@ -411,7 +411,7 @@ pub enum CmpOp {
     St(MergeFlag, RegA, Reg8),
 
     /// Inverses value in `st0` register
-    #[display("stinv")]
+    #[display("inv      st0")]
     StInv,
 }
 
diff --git a/src/library/lib.rs b/src/library/lib.rs
index 640b99c..9c2b9ca 100644
--- a/src/library/lib.rs
+++ b/src/library/lib.rs
@@ -435,6 +435,13 @@ impl Lib {
                     }
                     return None;
                 }
+                ExecStep::Fail => {
+                    registers.st0 = false;
+                    assert_eq!(registers.st0, false);
+                    #[cfg(feature = "log")]
+                    eprintln!("execution stopped; {d}st0={z}{r}{}{z}", registers.st0);
+                    return None;
+                }
                 ExecStep::Next => {
                     #[cfg(feature = "log")]
                     eprintln!();